VOGONS


First post, by Sphere478

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Related projects:Sphere's PCB projects.

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Re: Socket 5/7/SS7 (Voltage Interposer) Tweaker. (Beta) (scroll forward to make sure link isn’t out of date)

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Socket 5/7/SS7 Voltage and Tweaking Interposer

What is it?

This is the culmination of all the different socket 5/7 mods in one package.

What does it do?

-Allows the use of processors in motherboards with incompatible voltages. Via vcc2 tap.

-Enables the usage of BF0, BF1, BF2 and Intel BF2 for setting all possible multipliers supported by any cpu.

-Has the p5a 1.05/1.06 fix (enable/disable via switch)

-Tillamook mods. For l2 cache/voltage detect

-Vcc3 tap for motherboards without 3.3v supplies.

-Allows you to set 2.5v vio for tillamook processors (not really needed, but you can if you want to)

OP:
————————————————————
I know some of you including myself have been waiting for this for quite some time.

I have some learning to do, and it may take several prototypes but, I'm gonna try. And maybe with a little help, brainstorming, encouragement, and cooperation we can have a really great product in the end for all of us to DIY build and enjoy! :p

First off, I'm going to opensource this, I'll post incremental Files as the prototypes develop feel free to use them or modify them as you wish or see fit. (and at your own risk of course) but it is probably unwise to order/use any early versions that have not been prototyped in physical form and confirmed to be working without error.

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Last edited by Sphere478 on 2023-01-18, 03:40. Edited 27 times in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 1 of 221, by Sphere478

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CPU Mounting And Pins:
One major hurdle that will have to be overcome is how to attach a socket that also has pins that will plug into a socket below

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these can still be bought but are quite annoying to remove the processor once it has been inserted, also how do we expect to install proper heatsinks?

Which brings us to using ZIF sockets…

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But that has the issue of not working with the lever stops, and the issue of the pins being too short.

How has it been done in the past?

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this device shown above seems to be using a custom LIF with very long pins?

can we find LIF with longer pins though? I can't seem to find any.

another idea ,offset the socket:

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or maybe a two part pcb:

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personally though, I don't like options that extend the length of the cpu lines more than a socket stack.
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Do you guys have any ideas about how to turn a ZIF or LIF into a device that can solder into a board and still have pins long enough to still reach to the lower socket?

Last edited by Sphere478 on 2022-04-02, 09:12. Edited 2 times in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 2 of 221, by Sphere478

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Pin Routing:
pin schematic:

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here are the voltage pins

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here are the ones that need to be severed and powered separately:

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there are other pins of interest but they have been researched and are pretty well understood here:
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Socket 5/7/SS7 (Motherboard) Tweaker (Released)
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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 3 of 221, by Sphere478

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here is a variation on an above idea: two parts: solder the sockets first then use jumper pins to solder the two board parts together, but add connections to the interior of the socket also. it may be possible to use resistor legs for the pins to install into the board socket.

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I see two issues with this
-it lengthens the signals significantly, and may introduce interference
-it will make it not fit in quite a few motherboards with limited area around the socket

but it should be pretty straightforward to build... no super tricky soldering.

Apparently such a thing works on socket 3 in some capacity..

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Edit:
here is a interesting find:
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"QTY (10) 321 POSITION PGA SOCKETS 19x19 COLD FORMED 390094-1 AMP NOS 1 TUBE"

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this could solve the heatsink and lever problem
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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 4 of 221, by Sphere478

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okay, here we go, now we're talking...

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We could create the socket out of a bunch of these (and some of the shorter ones or simply trim some)
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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 5 of 221, by 0xCats

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You can't actually use these pin headers to create the sockets correctly
The pin spacing and diameter is not correct. They are also too thick and break the internal socket clasps.

But there is no need to use a janky pins of any sort at all.
Max-Mill PGA interstitial sockets already exist. (they are the same that the original powerleap etc designers used)
They can be stacked into another socket through a PCB.
The voltage pins can be removed from the interstitial to isolate it to just powering the CPU so as not to backfeed the mainboard VRM.

I already have a bunch for the "SoCat-57" adapter I'm making.

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There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 6 of 221, by Sphere478

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0xCats wrote on 2022-04-02, 11:02:
You can't actually use these pin headers to create the sockets correctly The pin spacing and diameter is not correct. They are a […]
Show full quote

You can't actually use these pin headers to create the sockets correctly
The pin spacing and diameter is not correct. They are also too thick and break the internal socket clasps.

But there is no need to use a janky pins of any sort at all.
Max-Mill PGA interstitial sockets already exist. (they are the same that the original powerleap etc designers used)
They can be stacked into another socket through a PCB.
The voltage pins can be removed from the interstitial to isolate it to just powering the CPU so as not to backfeed the mainboard VRM.

I already have a bunch for the "SoCat-57" adapter I'm making.
Interstitial sockets.jpg

DSC_0282.jpg
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oh awesome!

I ordered some of the top part, now I need to find that white part!

here is another thing I'm wondering about.

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how the heck to we keep this thing from hitting everything on the mobo 🤣
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edit:
okaay! good deal! Max-Mill PGA interstitial socket ordered!

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I got these both from ebay btw.
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Last edited by Sphere478 on 2022-04-02, 11:23. Edited 1 time in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 7 of 221, by 0xCats

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To add something more

A dual PCB design with headers between them is almost entirely unworkable. Here is why:
I ran a simulation of it and tried with just normal stacked sockets to find out how badly it affects system stability and reliability. How many sockets can I stack with the CPU still working.
It's safe to say from testing that even 2x1 sockets stacked is a problem if they are not completely tightly wedged into each other. The Kingston turbochip module actually soldered the two stacked sockets to resolve this.
Even just 2x2 stacked leads to glitches and a lot of EMI, crosstalk and other capacitive coupling problems.
But at 3x2 stacked sockets as seen above in my pictures it is a total mess at the 66Mhz FSB.
And this was with tightly stacked sockets, with 2.54mm pin headers plus PCB trace routing I expect it to be much worse.
It works on a 486 and such due to their low FSB and much lower signalling requirements.

But for Pentium, especially for the Host data bus and cache controls it needs to done right or just becomes real glitchy mess.

As for the socket spacing, this is something that's relatively easy to solve with modern IC's, all of the voltage regulation stage can fit inside the socket and over the unused socket lever/cover area.
With modern electronics this can be even smaller than the original Kingston TurboChip module:

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There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 8 of 221, by Sphere478

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0xCats wrote on 2022-04-02, 11:22:
To add something more […]
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To add something more

A dual PCB design with headers between them is almost entirely unworkable. Here is why:
I ran a simulation of it and tried with just normal stacked sockets to find out how badly it affects system stability and reliability. How many sockets can I stack with the CPU still working.
It's safe to say from testing that even 2x1 sockets stacked is a problem if they are not completely tightly wedged into each other. The Kingston turbochip module actually soldered the two stacked sockets to resolve this.
Even just 2x2 stacked leads to glitches and a lot of EMI, crosstalk and other capacitive coupling problems.
But at 3x2 stacked sockets as seen above in my pictures it is a total mess at the 66Mhz FSB.
And this was with tightly stacked sockets, with 2.54mm pin headers plus PCB trace routing I expect it to be much worse.
It works on a 486 and such due to their low FSB and much lower signalling requirements.

But for Pentium, especially for the Host data bus and cache controls it needs to done right or just becomes real glitchy mess.

As for the socket spacing, this is something that's relatively easy to solve with modern IC's, all of the voltage regulation stage can fit inside the socket and over the unused socket lever/cover area.
With modern electronics this can be even smaller than the original Kingston TurboChip module:
IMG20220111151235.jpg
IMG20220111151241.jpg

excellent!

question, how do we solder the two sockets together?

for my design I want to put the tweaks from my other project on it also so I want to find room for that. But something I absolutely hate about the old adapters is the switches being under the cpu that was so hard to pop out each time you wanted to change a setting.

-----------------------------------------------------------------------------------------

So far, my "desired" features list is this,
(Though some of these may never happen as many of them are of course asking a lot but I'll list them):

-A top of the line voltage supply for vcc2 that is more stable than can be found on any socket 7 motherboard from the factory. With a settable range between 1.4v-3.5v

- wt/wb pull up and pull down switches

-bf0, BF1, BF2, Tillamook BF2 pull up and pull down switches

-Tillamook cache mods with switchs

-Tillamook vccdet mod with switch

-Temp probe

-Temp/voltage display or at least a external sensor header for external reading. There are some very small devices these days with little oled displays like gotek and atx2at something like that may fit here? but is asking a lot. though may be possible..

-One of the old interposers had a feature where it would drop the multiplier based on temperature. (will cpus even respond to multiplier change in real time?)

-Cache would be cool, but I need to learn a lot before I'm there.

----------------------------------------------------------------------------------------------

micro or regular jumpers may be the answer to space constraints they could be along the edge of the socket flushagainst the socket down both sides using minimal space

Last edited by Sphere478 on 2022-04-02, 11:55. Edited 1 time in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 9 of 221, by 0xCats

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I think the easiest way to flexibly control all of them would be with a modern microcontroller on the PCB that can detect the CPU type, voltage, multi, detect the pin state and load and set specific pin configurations all without needing to fiddle any dip switches.

At least that is what I'm designing around 😉

There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 10 of 221, by Sphere478

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0xCats wrote on 2022-04-02, 11:53:

I think the easiest way to flexibly control all of them would be with a modern microcontroller on the PCB that can detect the CPU type, voltage, multi, detect the pin state and load and set specific pin configurations all without needing to fiddle any dip switches.

At least that is what I'm designing around 😉

oh wow, that's next level....

would we need a comprehensive database of cpus and settings to make that work? (programmed into the controller) like, people would have to report data from their cpus and it would be added to the firmware?

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so obviously this is a crude render but you think that shrinking the size to something near this level is possible? (seems too small, also no cache chip... but there is room inside the socket on the bottom also 🤣.
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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 11 of 221, by 0xCats

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Sphere478 wrote on 2022-04-02, 11:57:

would we need a comprehensive database of cpus and settings to make that work? (programmed into the controller) like, people would have to report data from their cpus and it would be added to the firmware?

Yes, but it's not too difficult to put together.

There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 12 of 221, by Sphere478

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0xCats wrote on 2022-04-02, 12:20:
Sphere478 wrote on 2022-04-02, 11:57:

would we need a comprehensive database of cpus and settings to make that work? (programmed into the controller) like, people would have to report data from their cpus and it would be added to the firmware?

Yes, but it's not too difficult to put together.

see edit^

Sphere’s socket 5/7 cpu collection.

I might be able to so some research to help :p it'll take a while though to catalogue all of them though... wow..

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 13 of 221, by 0xCats

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Created the Footprint + Symbol with all rule defintions 😁

Time to rock and roll

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There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 14 of 221, by 0xCats

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Sphere478 wrote on 2022-04-02, 11:45:

- wt/wb pull up and pull down switches

I just saw you wrote this, but controlling this line is not safe to do with pull resistors. It operates in unison with the PWT and KEN# signals.

See the documentation:

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This is a chipset controlled signal.

And from the AMD K6-2 documentation:

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So tying this pin Low or High externally from the chipset will lead to some very unpredictable results.

Really the WB/WT# signal is used for complex behaviour and it's necessary to be rapidly switched in operation for setting Cacheline states among other things.

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And again here the signaling logic for a Writeback Cacheline replacement. If the WB/WT is static locked either high or low your processor will have a serious problem
(Note the BRDY and WB/WT signals) and how they correlate to D[63:0].

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There are two types of devices, those that know they've been hacked and those that don't yet know they're going to be hacked.

Reply 16 of 221, by Sphere478

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0xCats wrote on 2022-04-02, 17:48:
I just saw you wrote this, but controlling this line is not safe to do with pull resistors. It operates in unison with the PWT a […]
Show full quote
Sphere478 wrote on 2022-04-02, 11:45:

- wt/wb pull up and pull down switches

I just saw you wrote this, but controlling this line is not safe to do with pull resistors. It operates in unison with the PWT and KEN# signals.

See the documentation:Screenshot_20220402_194350.jpeg
This is a chipset controlled signal.

And from the AMD K6-2 documentation:
Screenshot_20220402_194635.jpeg
Screenshot_20220402_194702.jpeg

So tying this pin Low or High externally from the chipset will lead to some very unpredictable results.

Really the WB/WT# signal is used for complex behaviour and it's necessary to be rapidly switched in operation for setting Cacheline states among other things.
Screenshot_20220402_195053.jpeg

And again here the signaling logic for a Writeback Cacheline replacement. If the WB/WT is static locked either high or low your processor will have a serious problem
(Note the BRDY and WB/WT signals) and how they correlate to D[63:0].
Screenshot_20220402_195412.jpeg

Re: K6-2/3+ Success on Asus P5A 1.06 - simple mod
It’s been proven safe. And working on asus p5a

Not saying you are wrong, something done in that thread is helping. Maybe there is a better way to do it?

0xCats wrote on 2022-04-02, 18:22:

The same will apply for your BRDY, & ADS# pins.

there is a thread about those also. If you have a better way I can maybe redesign the tweaker.
Re: Tillamook 266MHz and working L2 cache?

Those are shorted with other pins to do their respective mods. (In the thread, they direct short them) my tweaker pcb allows use of a switch and resistor should it be desired.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 17 of 221, by Sphere478

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Strange Socket 7 "mod"

Speaking of mods, may have missed one, this post^, if I counted my pins right seems to be doing two mods (one a known tillamook mod) and also a unknown one..

What do you make of this Oxcats

Cats, do you think that the cache chip you have spoken of could fit between the pins under the pcb?

How is the motherboard cache overriden? Severing of select pin signals to the mothetboard? Can the on interposer cache still be disabled via bios? Or will that need to be done on interposer?

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hmmmm....

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 18 of 221, by Sphere478

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let's see,

Alpha 1

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here is the result of my tinkering (and dreaming) Oxcats: feel free to use any or all of this. maybe the edge cut may be useful. (I based the tabs on included socket diagram)

Edit: Alpha 2

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http://db.zmitac.aei.polsl.pl/Electronics_Fir … ex/29746702.PDF
so I'm guessing the cache attaches to the host bus but doesn't matter where. and the pins on the cpu for the bus are as good of place as any. and to disable motherboard cache we just divorce a few select pins and presto, the cache on the interposer is now the active cache? am I following this right?

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Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 19 of 221, by Sphere478

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I found another way it was done:

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Edit:
Alpha 3

Filename
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    Schematic.png
    File size
    231.97 KiB
    Views
    3395 views
    File license
    Public domain
  • front 3D.png
    Filename
    front 3D.png
    File size
    386.53 KiB
    Views
    3395 views
    File license
    Public domain
  • back 3D.png
    Filename
    back 3D.png
    File size
    396.65 KiB
    Views
    3395 views
    File license
    Public domain

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)