VOGONS


Reply 20 of 27, by mkarcher

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feipoa wrote on 2023-05-08, 12:49:

If I made a mistake, I don't know where.

Seems like my edit wasn't clear enough or too late. I still maintain that WB/WT# should be connected to JP8, pin 6, but it is also connected to JP13, pin 3.

You use JP13 to connect that pin to the reset line for classic Cyrix soft reset, but you use JP8, pins 5 to 7 to pull the pin up or down for &EW cache mode selection or NV8T multiplier selection.

Reply 21 of 27, by feipoa

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I did not see your edit. The continual edits in this thread have made it hard for me to follow.

JP8, pin 6 does not go to WB/WT#. There is a 4.7 K-ohm resistance path between JP8, pin 6 and WB/WT#.

Before I posted my comment concerning JP13, pin 3 being WB/WT#, I had already checked all the CPU jumper pins to see if any other pins on the header went to WB/WT#. Only JP13, pin 3 on the CPU jumper block is connected directly to WB/WT#.

Plan your life wisely, you'll be dead before you know it.

Reply 22 of 27, by pshipkov

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I don't feel proud of my contribution to this thread, so thanks for putting up with it.

We have to topics mixed-up.

1. My problem that i started the thread with AWE64 Gold having problems in DOS when L1 cache is in WB mode.
2. Your problem, where Yamaha OPL3 based card is having problems at 3x60MHz with no PCI bus divider.

As for setting the L1 cache in WB mode - the other day i used a simple interposer that allows me to disconnect the corresponding pin and set the L1 cache policy right in front of the CPU.
I tried before then to figure out which jumper is supposed to set the L1 cache policy, but my brief attempt on the weekend failed, so didn't waste more time and simply used the interposer. Maybe i missed something obvious. Did you find which jumper does it ?

retro bits and bytes

Reply 23 of 27, by mkarcher

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feipoa wrote on 2023-05-09, 00:11:

I did not see your edit. The continual edits in this thread have made it hard for me to follow.

So my edit was too late. I will try to get used to making a new post instead of editing if I have to add significant new information, and maybe just edit a hint to the new post into the old post (so readers of the old post won't miss the new information. Sorry about that.

feipoa wrote on 2023-05-09, 00:11:

JP8, pin 6 does not go to WB/WT#. There is a 4.7 K-ohm resistance path between JP8, pin 6 and WB/WT#.

So, your measurements were accurate. On the other hand, JP8, pin 6 is still meant to control the level of WB/WT#. I expect JP8 pin 5=GND and pin 7=Vcc, so the jumper settings in the manual make sense. For statically pulling up/down WB/WT#, a 4.7K resistor is good enough and considered "good practice". On the other hand, for the dynamic function "soft reset" of the classic Cyrix 486 pinout, that pin needs sharp edges, which requires the signal to be connected to pin B13 without any kind of resistor.

feipoa wrote on 2023-05-09, 00:11:

Before I posted my comment concerning JP13, pin 3 being WB/WT#, I had already checked all the CPU jumper pins to see if any other pins on the header went to WB/WT#. Only JP13, pin 3 on the CPU jumper block is connected directly to WB/WT#.

So the lesson learned (also for me, I would have measured exactly the same way at first): For jumpers that pull a pin up or low, a continuity check is not sufficient to find them, because a resistor might be between the jumper and the CPU pin.

Reply 24 of 27, by mkarcher

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pshipkov wrote on 2023-05-09, 05:45:

Did you find which jumper does it ?

While I won't give you a 100% guarantee, the findings I gathered from the manual and the measurements taken by feipoa strongly suggest that on the Rev D board, the L1 cache mode jumper for AMD 5x86 processors (and Intel 486DX2/DX4 &EW processors) is JP8, pin 6-7. Remove that jumper to get WT.

Reply 25 of 27, by feipoa

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pshipkov wrote on 2023-05-09, 05:45:
I don't feel proud of my contribution to this thread, so thanks for putting up with it. […]
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I don't feel proud of my contribution to this thread, so thanks for putting up with it.

We have to topics mixed-up.

1. My problem that i started the thread with AWE64 Gold having problems in DOS when L1 cache is in WB mode.
2. Your problem, where Yamaha OPL3 based card is having problems at 3x60MHz with no PCI bus divider.

On the contrary, my DOS sound problem occurs only when a PCI bus divisor being used. If PCI = FSB, I have no problem. As for your problem, it sounds like you have a problem with DOS sound with and without the PCI divisor. I suspect the two issues are related somehow.

mkarcher wrote on 2023-05-09, 06:19:

So the lesson learned (also for me, I would have measured exactly the same way at first): For jumpers that pull a pin up or low, a continuity check is not sufficient to find them, because a resistor might be between the jumper and the CPU pin.

Indeed, some motherboards have a direct connection from socket 3 WB/WT# to a jumper pin, while it seems others wired it in the other direction.

mkarcher wrote on 2023-05-09, 06:24:

While I won't give you a 100% guarantee, the findings I gathered from the manual and the measurements taken by feipoa strongly suggest that on the Rev D board, the L1 cache mode jumper for AMD 5x86 processors (and Intel 486DX2/DX4 &EW processors) is JP8, pin 6-7. Remove that jumper to get WT.

I'll check this in the next little bit.

Plan your life wisely, you'll be dead before you know it.

Reply 26 of 27, by feipoa

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I can confirm that removing the jumper from JP8, pins 6-7 sets the Am5x86 into L1:WT mode. Thanks a lot; saved me some probing work! Now let me see if I can replicate pshipkov's symptoms.

Plan your life wisely, you'll be dead before you know it.

Reply 27 of 27, by feipoa

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I tried to replicate pshipkov's workaround methods for getting DOS sound working by a) setting L1 to WT, and b) disabling L1 entirely. I tried using an AWE64Value and an OPL3 card with the 1/2*FSB divisor enabled for PCI, but still DOS sound will not work, whether or not I set L1 to WT, or disable L1. I tried the ISA bus on 7.159 MHz, on PCI/3, and PCI/4. Alternately, if I set PCI = FSB, I have no problem with DOS sound with L1:WB mode.

I find it strange that pshipkov is able to use sound in Windows (and DOS when L1:WT) when PCI = 1/2*FSB, yet I am not. Why would his system's 1/2 CPUCLK divisor be working a bit better than on my board? Could you let me know the exact markings on your PLL chip? Mine are:

MX8325-1MC
MDZD41028
B9643 TAIWAN

As for your issues with sound in DOS, perhaps try something based on the Yamaha YMF718-S chip, preferably without the IDE connector. I don't have any issue with DOS sound using this card, provided that PCI freq = FSB via JP16. Considering your symptoms, with any luck, you may be able to get DOS sound working with this card, even if you have PCI = 1/2*66.

Plan your life wisely, you'll be dead before you know it.