This is what happens on the i430fx:
https://www.dropbox.com/s/14nnfxvsymhexv9/deb … Instead.7z?dl=0
Can anyone see why it's rejecting the PCI IDE and selecting the onboard only (and perhaps why it's giving the error of conflicting devices)?
Edit: Hmmm... At eb8e:00002f8f 80 FD 03 cmp ch,03
CH is the class code, CL is the subclass, both read from the PCI space of the PCI IDE controller.
It then tries to clear BAR0 by writing it with zeroes.
Then it arrives at:
eb8e:00002ffb 83 C7 04 add di,0004
So, f000:0000e008 AH=1D clears the BAR selected by DL.
That's at eb8e:00002ff6 9A 08 E0 00 F0 call f000:0000e008
Said calls all return at eb8e:00002ff6.
When it's processed all BARs, it arrives at "eb8e:00003003 BF 30 00 mov di,0030".
It clears bar at address 30(the ROM bar), then proceeds to call AH=1B on said function handler. DI=3C in this case.
That's at eb8e:00003012 9A 08 E0 00 F0 call f000:0000e008
OK. So function 1B writes CL to the byte register specified by DI.
Then, at 301A, it specifies function 1C instead. DI is set to 4.
It calls the function at:
eb8e:0000301c 9A 08 E0 00 F0 call f000:0000e008
OK. So that function writes CX to the specified 16-bit register specified by DI. BL seems to be device and function number in the second byte of the PCI CF8 register.
It then reaches:
eb8e:00003021 BF B9 32 mov di,32b9
I see it scanning some values 05,00,40h(it keeps matching 10h on this one) in memory, with a limit of 12 bytes being scanned?
Edit: So, so far, the following functionality of function f000:0000e008 has been found:
AH=0D, unknown. Checks some data and eventually returns giving AL=01h.
AH=18 read 8-bit PCI to CL BL=devfn, BH=busnr, DI=addr
AH=1A read 32-bit PCI to ECX BL=devfn, BH=busnr, DI=addr
AH=1B writes CL to the byte register specified by DI. BH=busnr, BL=devfn, DI=addr
AH=1C writes CX to the specified 16-bit register specified by DI. BL seems to be device and function number in the second byte of the PCI CF8 register.
AH=1D writes ECX to the specified 32-bit register specified by DI. BL=devfn, BH=busnr, DI=addr
AH=26 Some internal logic? Selects devicefn 38(device 7 function 0), position 60 and writes 0Eh to it? Looks like some kind of IRQ assigning function? Sets the IRQ number to CL(0Eh), then sets said bit in the ELCR. and returns to the caller.
AH=28 AL=01 read F000:6B2E and compare with AL. If matches, give F000:6B20 and return on BX, with 8-bit flipped?
Function 26 is kind of complicated. It reads some tables and based on BL and DL, writes AH to PCI register 60 based on that and sets said bit in the ELCR. That might be the PCI INTA# setting that it's expecting somehow?
What I see it do with the AH=26 handler:
6B20=BX? Then go to 6C8A
AL(60h)? STC and jump to 6C6C if not. Not taken.
AL top 4 bits set? Not set, reaching 6c68. calls 6BDE.
bus 0 offset 60 devfn 38 selected. 0F(input AL) written to it.
CL=input AH. Set said bit in the ELCR.
Edit: Hmmm.... I see something interesting ther: devfn 38 is device 7 function 0. It doesn't match any existing hardware in the emulation. But guess what's related to the ELCR and matches said register 60h? The PIIX chip that's on said motherboard!
So instead of it's location on the i430fx is hardcoded at device 7 for the PIIX?
Edit: Hmmm... Said devfn 38h is from "cs:[d64f]"?
Edit: After scanning the PCI IDE's BARs, it arrives at eb8e:00003c1c...