The SLDIV and SD bits in the CRTC registers seem like they do the same(in UniPCemu, they're currently stacked together to divide the scanline input by 1,2 or 4 to calculate the row to index into the vertical character grid(which makes a character/inner character row out of that input).

So with a character height of 2, row 0 becomes 0.0. row 1 becomes 0.1, row 2 becomes 1.0, row 3 becomes 1.1 etc.. In the format row.innerrow, in much the same way horizontal timing works with character.innerx(where innerx is between 0-7 or 0-8, depending on the dot clocks per character).

Now, the freeVGA documentation says that:

SD -- Scan Doubling
"When this bit is set to 1, 200-scan-line video data is converted to 400-scan-line output. To do this, the clock in the row scan counter is divided by 2, which allows the 200-line modes to be displayed as 400 lines on the display (this is called double scanning; each line is displayed twice). When this bit is set to 0, the clock to the row scan counter is equal to the horizontal scan rate."

And:

SLDIV -- Divide Scan Line clock by 2
"This bit selects the clock that controls the vertical timing counter. The clocking is either the horizontal retrace clock or horizontal retrace clock divided by 2. When this bit is set to 1. the horizontal retrace clock is divided by 2. Dividing the clock effectively doubles the vertical resolution of the CRT controller. The vertical counter has a maximum resolution of 1024 scan lines because the vertical total value is 10-bits wide. If the vertical counter is clocked with the horizontal retrace divided by 2, the vertical resolution is doubled to 2048 scan lines."

Since the row scan counter(the row as mentioned for the input to the vertical character.innercharrow format) always runs at the same rate as the horizontal retrace clock(ticked up to the next line by htotal being reached in UniPCemu's VGA renderer), what's the difference between the two settings?