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Reply 1900 of 1900, by TheGreatCodeholio

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ripsaw8080 wrote on 2020-04-28, 10:41:
TheGreatCodeholio wrote on 2020-04-28, 08:10:

the LSB masking only affects reading the counter.

Yes, but the question is if it should apply when the counter is written. I realize it would halve the number of possible frequencies that can be selected, but the difference is perhaps small enough to be indistinguishable. It seems more like what the hardware would do than making a special case of a counter value of 1.

According to Intel's documentation, there does seem to be somewhat different handling for even and odd values. Though it always counts by 2 and counts down from an even value the documentation implies that there is a one cycle delay before it reloads the counter every other countdown.

Reading the documentation says that for mode 3, it would seem the counter is loaded with the value with the LSB removed and counted down by 2 for each half of the square wave. Note that if you do that with 1 or 0 it comes out 0, which then means the longest period possible. So it's probably not much of an addition to silicon at all. The documentation seems to imply the first half of the square wave has one additional clock cycle of delay before reloading and going LOW to start the process again, if the initial counter was an odd value.

http://hackipedia.org/browse.cgi/Comput ... 9%29%2epdf

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