No ideas? Well, I see I haven't really asked reasonable questions 😀

486 is ... above my know-how (tried some time ago, it's too much for me - though my first home PC was 486, I actually never bothered to even swap my DX2-66 - I only upgraded RAM from 4 MB to 20 MB 😀 ). I'm gonna run it "stock", more or less - no tweaking, no countless hours in tests. I want Windows 98SE (running as fast as possible with max RAM, cached or not cached ...) and some old games like ... Dune II, Transport Tycoon Delux, Mortal Kombat, Raptor, etc ...

Yet, I want to try the Am5x86 at 40FSB (it might actually run at 160Mhz, who knows). Even more - I would try to go for 200Mhz if I get the suitable CPU some day. (I remember a topic from this forum).

But I see no options for raising the CPU Voltage in the manual I have. So I'm curious how could I set it up to 3.5-3.6Vs?

Please review these two topics on this board,
Help with SiS 496/497 Tomato 4DPS 486 motherboard
AMD x5 133 - the Mystery of Abysmal Performance

Remember for WB L2 cache, set the TAG bit to 7. For WT L2 cache, set the TAG bit to 8.

My conclusion with this board was that is does not benefit a whole lot from 40 MHz operation compared to some other boards because I needed to reduce the memory speed by way of the cache write cycle to obtain a stable system. When the cache write cycle is set to 3 for stable operation, the cachechk main memory speed fell to about what it would be at 33 MHz. You do, however, still get the faster L1 and L2 speed as expected for an AMD X5-160 though. I am not sure if the instability at 40 MHz is due to 512 KB cache size I was using or if it is due to the single-banked nature of this board. In general, 256 KB of double-banked L2 cache seems to be the most forgiving with the fastest memory/cache CMOS settings.

Attached is the funworld 172f BIOS with the funworld logo remove from boot screen. I may have also rearranged the location of some of the CMOS entries to fit my preference.

A Voodoo3 does work with this board, however I recall some strange problems with it at 40 MHz. At times, the board would appear dead if I changed and saved the CMOS settings. I would have to pull all the cards out and discharge the CMOS for it to work again. This problem (and solution) was not always repeatable.

Does anyone know if the Voodoo3 or the Banshee is less problematic with a 40 MHz FSB?

Has anyone compared a Voodoo3 to a Banshee on a 486 using Quake or GLQuake?

Your previous BIOS mod has been already up on Vogonsdrivers for a while 😀 The logo-free version might appeal more to some ppl, though.

I have a Banshee only, it never gave me the glitches you described (neither with a 120 Mhz Cyrix nor the 160 Mhz AMD). But I did not test it extensively.

feipoa wrote:

Please review these two topics on this board,
Help with SiS 496/497 Tomato 4DPS 486 motherboard
AMD x5 133 - the Mystery of Abysmal Performance

Thanks feipoa

I did encounter the first topic in google but the second one has escaped the search 😀

Single banked vs double banked cache is unknown to me. What does it stand for?

Anyway, I'll give a try to the 40Mhz

Btw, due to a lack of cache, my best chips shoud be those 256K of UM61512AK-15 I already plugged in. This mean I'll have 32MB of cached RAM. I could use 2x32MB sticks and make the upper half a RAM disk, but I wonder what would perform better under Windows 98SE. Having only 32MB of cached memory, or the total of 64MB, half of it uncached?

feipoa wrote:

Remember for WB L2 cache, set the TAG bit to 7. For WT L2 cache, set the TAG bit to 8

Thanks, I have missed it in the manual (it's on two pages 😀 ), now I saw it. The CPU is a 133ADW so it would be in WB.

You can set the L2 cache to Write Thru (WT) and have 64 MB of cacheable RAM with only 256 KB of L2 cache. The performance hit is fairly minimal.

Jolaes76, are you refering to BIOS 4DPS400A? I've had trouble with that BIOS version.

Space Cowboy, double-banked cache, in this context, uses 8 chips for, say, 256 KB instead of 4 chips for 256 KB. Double-banked operation may allow for cache interleaving which increases performance. The main advantage, however, is that I have noticed 256 KB, double-banked cache, seems to accept faster cache/memory CMOS timings.

Jolaes76, what are your cachechk results at 160 MHz and what CMOS settings are you using?

I recall I wrote in a thread somewhere on Vogons which instructs how to set variable CPU voltages on the 4DPS. One resistor gets removed and a trimmer put in its place. The mod is very easy.

Space Cowboy,

the AMD 5x86 has write-back L1 cache, but setting L2 cache to WB as well is not necessarily results in better performance (depending on your configuration) and in general, most systems are more stable with L1 WB + L2 WT combination. At least this is my observation reading thru a lot of OC reports. I measured load and response times in Windows 98SE Lite long ago but I remember that having more RAM, even if some of it uncached is a far better option than having much less but fully cached RAM.

feipoa,

unfortunately the Zida is not with me ATM and I have only made notes of the current config - it has the Cyrix running at 3x40 Mhz now, not the 160 Mhz AMD. Cannot be a point of reference to the OP. Sorry. But from memory, the Zida scored only marginally better than the same CPU + RAM in the Asus VL/I 486 SV2GX4.

feipoa wrote:

I recall I wrote in a thread somewhere on Vogons which instructs how to set variable CPU voltages on the 4DPS. One resistor gets removed and a trimmer put in its place. The mod is very easy.

Thanks, I'm gonna search it.

Jolaes76 wrote:

the AMD 5x86 has write-back L1 cache, but setting L2 cache to WB as well is not necessarily results in better performance

Both of you are perfectly right. I was thinking of "squeezing" max perfomance, and I have not considered that L2 WT might be actually the better option.

One thing, that I haven't thought of, but I start to grow for (with reading), is that 486 system as a whole should benefit far more from a tigtened cache/ram operation cycles, rather than pure CPU computing power.

I might have already asked the question in the topic for my other 486 (the one I actually had back then) a few months ago, but I don't remember if anyone has answered - in a situation like this:

If I fill only half of the cache slots (I have 4 x 32K8 and a corresponding tag ram), would I see problems with the cache?

I suppose this is the "double banked" scenario, and I wonder wif it will work OK?

BTW, feipoa, do you happen to know, if I can edit the BIOS of this board (SIS 471) to correctly recognize Am5x86. It's a phoenix BIOS ... I thought I could use cbrom for example (or other tool), to release that part of the BIOS, that contains the microcodes for the CPUS, and add a richer list. But probably these BIOS-es do not have the structure of more modern one. I have used cbrom in the past, to update my SATA controllers BIOS (part of the board's BIOS), and I've seen sources in the net, that use it for updating the cpu support - it was a simple procedure ...

It's just cosmetic, cause there is a jumper on the board, that is supposed to set the "internal" cache to WB/WT (that is to be the L1, I beleive), so I can force it anyway.

Using a single bank configuration is standard, you should not have problems with that (other than non-optimal performance).

I have not modified a BIOS to allow for proper CPU detection; can't help you there.

The majority of motherboards I have come across which have 8 cache DIPs sockets tend to use the double-banked (8 chips) configuration. I have only taken note that when using more than 256 KB cache, it is sometimes a requirement to reduce the L2 cache timings in CMOS. This is especially true when going from 256 KB, double-banked, to 512 KB, single-banked. 1024 KB, double-banked, also seems to prefer slower L2 cache timings. I have not done a comparison of 256 KB double-banked, vs. that of 256 KB single-banked. It could be that need to reduce L2 cache timings are more dependent on the size of your L2 cache instead of single vs. double banked operation. It could also be that single vs. double-banked operation still plays a role in the need to reduce L2 timings but to a significantly lesser extent.

At one point I was working on all this characterisation on several different motherboards and different 486 chipsets. I had several hundred data points on a spreadsheet, but the issues became further complicated as different CPUs, FSB settings, cache amounts, and even the amount of RAM installed all had different requirements for the maximum usable L2/memory CMOS settings. Then I would need to run Memtest and wait hours for a failure. For any given CPU, it was usually a certain Memtest test # which would fail, but for a different CPU, it would be a different test #. It all began taking way too much time.

The main thing I learned from these experiments were:

• The more L2 cache (e.g. 1024K vs. 256K), the more system memory (e.g. 128 MB vs. 32 MB), or the faster the FSB (e.g. 40 MHz vs. 33 MHz), the more sensitive the L2 timings will be. The timings in these situations may need to be reduced from the most optimal CMOS settings for a truely stable system.
  
  The faster or more advanced the CPU is per clock, i.e. a Cyrix 5x86-120 vs. an AMD X5-120 or AMD X5-160, the more sensitive the L2 timings will be. The timings in these situations may need to be reduced from the most optimal CMOS settings for a truely stable system. Some systems, for example, may just barely be stable with an X5-160 at the most optimal CMOS settings given your amount of L2 cache and memory, but not with a Cyrix 5x86-120.
  
  Having more memory per stick and using less SIMM slots seems to allow for faster L2 timings.
  
  The most optimal CMOS settings may also be BIOS revision dependent. I have found that using a 4DPS BIOS on a DTK board allowed for using 64 MB SIMMs, while the DTK BIOS did not. Recall from above that using less SIMM slots and denser memory sticks allowed for faster timings.
  
  Single-banked vs. double-banked cache may have an effect on how tight you can set your L2 timings. It may also be cache size-dependent, however the effects of single- vs. double- banked cache have not been studdied w.r.t. a common overall L2 cache size.

Keep in mind that your requirements for a stable system may be less stringent than mine. If you are OK with Windows 98 crashing during installation, or having failed memory on Memtest, then you might be able to get away with tighter CMOS settings.

Hm, people, I can't really understand the L2 cache situation:

1) What should be the TAG RAM size chip in any given situation? Same as all of the other chips?

I mean, if I have 4 x 32Kx8, the tag ram should be 32Kx8 too? And what if I have 8 x 32Kx8? What should be the tag ram size?

2) why the tag ram has 28 legs? (it leads us to question 3)

3) I have three 486 boards, and two of them are BABY AT, so the cache is in 4 + 1 configuration. My third board has 8+1 sockets (the picture above), but all of the chips have 28 legs. Still, it says 32Kx8 on the sockets with 28 legs.

Could I use 32Kx8 chips (with 32 legs), and in what orientation? Or should I search for 28 legged chips.

Again: what should be the size of the TAG ram - same as one of the other chips? (I mean - 32Kx8? ) If I fill only 4, or all 8 sockets?

Thanks

This image taken from the HOT-433 manual should answer your questions concerning TAG and cache chip sizes.

32K x 8 - these are the 28-pin chips with '256' or '257' written on the surface.
64K x 8 - these are the 32-pin chips with '512' written on the surface.
128k x 8 - these are the 32-pin chips with '1024' written on the surface.

SingleBank - uses 4 chips
DoubleBank - uses 8 chips

There is one socket which is for the TAG chip. It should have "TAG RAM" or similar written on the PCB. Yes the orientation is very important. If you put them in backwards, they will short out and you'll likely fry the chipset, some component on the board, or the cache itself. The orientation is determined by the direction of the writing on the cache chip and the half circle notch on the cache module.

Thanks a lot. Got the idea. Now I understand why the TAG ram is DIP28.

I ran through my cache chips, and found that I have 3 sets of 256K cache + appropriate tag rams. (one came from a Socket 7 board with mixed both COAST and DIP cache).

And I'll need to find 9 pieces of 32K x 8 for my OEM 486.

Space Cowboy wrote:

And I'll need to find 9 pieces of 32K x 8 for my OEM 486.

That is correct. But you also need to set the jumpers correctly on the motherboard for double-banked 256 KB.