swaaye wrote:

mockingbird wrote:

K6-3+ is just a die shrink of the K6-III

Not quite. The + chips have 3DNow Extended like the Athlon.

I stand corrected.

mockingbird wrote:

Yes, but you clearly state in the video that you are only caching 128MB of RAM. That means your GA-5AX doesn't have a Revision G chip.

I disable the motherboard cache and it has bugger all impact. Basically once you have on-CPU cache, it doesn't matter what chipset / amount of cache / cacheable area you have. It has minimal impact.

And if you're talking about the K6-2, you might get a few % out of caching 512 MB, but the chip will still be behind the ones with on-die cache. Also, such boards usually support chips with on-die cache, so I don't see the point in sticking with the K6-2.

philscomputerlab wrote:

mockingbird wrote:

Yes, but you clearly state in the video that you are only caching 128MB of RAM. That means your GA-5AX doesn't have a Revision G chip.

I disable the motherboard cache and it has bugger all impact. Basically once you have on-CPU cache, it doesn't matter what chipset / amount of cache / cacheable area you have. It has minimal impact.

I know, but then you do not have a fair comparison between the K6-2 and the K6-3. K6-2 without on-board cache means no L2 cache at all. With the K6-3, since the on-board L2 cache becomes L3-cache, disabling it doesn't really affect it.

Your 128MB benchmarks are very telling though. When all systems only have 128MB of RAM, the K6-2 is almost on-par with a K6-2+. Not a slouch at all when paired with the right hardware.

How many boards have support for 512 MB caching area?

I just feel, if you board supports it, there is no reason not to go with a K6-2+ or K6-III+. Performance aside, you also end up more energy efficient, cooler and quieter as well as the ability to change the multiplier on the fly.

philscomputerlab wrote:

How many boards have support for 512 MB caching area?

I just feel, if you board supports it, there is no reason not to go with a K6-2+ or K6-III+. Performance aside, you also end up more energy efficient, cooler and quieter as well as the ability to change the multiplier on the fly.

Good point, but the K6-2 500 is less than the K6-2+ 500 ($5-$10 vs $15-$25) and much more commonly available.

I wonder if anyone has tried more than 768mb with the P5A 1.06 or the P5A-B 1.05 since the Aladdin V revision G is capable of caching up to 4GB.

swaaye wrote:

mockingbird wrote:

K6-3+ is just a die shrink of the K6-III

Not quite. The + chips have 3DNow Extended like the Athlon.

Did anything ever use them? 😁

Also Athlon had also some istructions more didnt it?

Athlon support MMX extended (sometimes also called MMX2)... which is in fact subset of SSE.

mockingbird wrote:

I wonder if anyone has tried more than 768mb with the P5A 1.06 or the P5A-B 1.05 since the Aladdin V revision G is capable of caching up to 4GB.

Had 1.5gb in a computer, last week, trying to install Win98se on it. Win98se game me an error, telling me that it had not enough memmory.
Silly me. Forgetting to check how much memmory the machine has before installing 98.
4gb is more like for WinXP and 2000. On the other hand, the K6-III is somewhat underpowered for XP. Wich then again, makes 4gb support indifferent as a feature. At least for me. Perhaps it is a plus in other people's book.

386SX wrote:

Did anything ever use them? 😁

Also Athlon had also some istructions more didnt it?

Yeah as said the Athlon also has integer SSE. The + chips have just 5 new "DSP" oriented instructions. I think DVD software uses them. To what benefit I have no idea. DSP oriented also makes me think of software modems which were coming out en masse back then.

swaaye wrote:

386SX wrote:

Did anything ever use them? 😁

Also Athlon had also some istructions more didnt it?

Yeah as said the Athlon also has integer SSE. The + chips have just 5 new "DSP" oriented instructions. I think DVD software uses them. To what benefit I have no idea. DSP oriented also makes me think of software modems which were coming out en masse back then.

IIRC, SSE was added with the Palomino core.

gdjacobs wrote:

IIRC, SSE was added with the Palomino core.

The floating point portion was.

Floating point (single precision) was what SSE registers were for. The integer elements you mention were just minor modifications of MMX.

brostenen wrote:

Had 1.5gb in a computer, last week, trying to install Win98se on it. Win98se game me an error, telling me that it had not enough memmory.

You had 1.5GB with a K6-2?

I tried two 512mb SDRAM modules in my P5A last night. One of them was only recognized as 256MB and it wouldn't boot with the other.

With 768MB, Memtest 86+ is taking 3 hours or so to complete 1 test cycle. Is that right?

Max ram for 98 is 512mb from what I remember...

I don't know if there are 512MB modules that would work on Aladdin V. 512MB DIMMs usually use a more dense DRAM that the late '90s chipsets can't handle.

gdjacobs wrote:

Floating point (single precision) was what SSE registers were for. The integer elements you mention were just minor modifications of MMX.

Yes but Intel lumped it all together with SSE branding as far as I know. Athlon had the integer extensions, but no fp until Athlon XP.

In response to mockingbird's concerns about leaving L2 enabled when using K6-III or + chips - I have found that some motherboards, particularly 430TX boards, allow for running tighter memory timings when L2 is disabled. In this sense, there is a performance benefit in disabling the L2 cache.

This is particularly true when trying to max out the RAM capacities of a particular chipset. In the case of my 430TX system with a K6-3+ chip, I could either leave L2 enabled and run only a 66 Mhz FSB with 256 MB RAM (K6-3-400) w/fastest RAM timings, or disable the L2 cache (by removing the DIP TAG chip) and run with an 83 MHz FSB and 256 MB RAM w/fastest RAM timings. Extensive tests for stability were done and I am confident with this conclusion. Note that FPM RAM must be used over SDRAM at 83 MHz & 256 MB RAM for complete stability. If you use SDRAM, it will be pseudo-stable only.

feipoa wrote:

In response to mockingbird's concerns about leaving L2 enabled....

More like how much faster really is the K6-3 compared to the K6-2 when the K6-2 is used on an Alladin V "G" Revision.

And I have some preliminary data (K6-2 500 @ 550, Asus P5A Revision 1.06):

Phil, I have my test rig set up. Can you please advise me on the best method of running benchmarks to compare against your results?

edit: Ok, it's not looking so good for the K6-2 so far. For PCPBENCH /VGAMODE I got an almost identical result (134.3) to yours (134.6). But as expected, I did NOT get that enormous decrease in performance with more than 128MB of RAM. So the Revision G is indeed caching all the RAM.

So the preliminary result shows that the on-die cache does indeed give an appreciable boost to the K6-3 in integer apps. I'm curious to see K6-3 scores in Speedsys compared to my K6-2. I'd also like to do some 3D benchmarks, but I haven't got a Voodoo 3 3500. I Right now I have a GeForce FX 5700LE in the board, and I've got a few other cards (Radeon 9700, GeForce 4 MX 420, TNT2 M64, GeForce 2 GTS, etc...)

swaaye wrote:

gdjacobs wrote:

Floating point (single precision) was what SSE registers were for. The integer elements you mention were just minor modifications of MMX.

Yes but Intel lumped it all together with SSE branding as far as I know. Athlon had the integer extensions, but no fp until Athlon XP.

I think it's not entirely clear what 'SSE' is, and what isn't.
I recall Intel talked about 'KNI': Katmai New Instructions.
This included new instructions that worked on the MMX registers, and also a new set of registers, with floating point operations.
I would say that SSE is only the part that works on the new registers, which is float-only. But the new MMX instructions are what AMD added to the Athlon (they didn't have the SSE registers. 3DNow! worked on the MMX registers, which is also the FPU stack).
But it could be that people refer to all of KNI with 'SSE'.

With SSE2 they added the ability to run the 'MMX' instructions on the wider SSE registers.

If you look at my CPUInfo project code: http://sourceforge.net/p/cpuinfo/code/ci/defa … /CPUInfo.c#l342
At line 1136 I set the MMXExt flag on CPUs that support SSE. This is done so that both Athlons an PIII CPUs will report MMXExt, so I can use it in applications, because only AMD makes the distinction.
There are some other bits that are different between AMD and Intel, which I fix in a similar fashion.