VOGONS


First post, by majestyk

User metadata
Rank Oldbie
Rank
Oldbie

The DFI K6XV3+/66 is a great socket 7 mainboard and I used it in one of my office PCs for years. For no obvious reasons most of the sold mainboards of this model had 512K onboard cache, a few had 2MB (unlike the baby-ATX version that came with 1MB or 2MB more often).

I decided to upgrade one of my 512K boards with a second 512K chip. After soldering the additional chip I intended to have a look at some picture on the web to find out about the jumpering (=positioning of the 0 Ohm resistors) for this configuration, because I only own 512K and 2MB versions.
I was surprised to find next to nothing - loads of 512K boards and a few blurry ones of the 2MB version.
So I had to find out myself. Here are the results:

K6XV3_1a.JPG
Filename
K6XV3_1a.JPG
File size
449.5 KiB
Views
173 views
File license
Fair use/fair dealing exception

Resistors R111, R112 and R113 are just for adjusting the cache size shown in the BIOS summary screen (and maybe tell the MCH what cache size to expect).
R111 -> 1024K
R112 -> 2048K
R113 -> 512K

But that´s not all. For 512K the address line A14 of the 32Kx8 TAG chip is grounded by R134 (the one at the bottom of the red circle).
For a cache size of 1Mb this resistor has to be moved to position R133 (the one above R134) to connect it to the MCH.
This is all that´s to be done for 1MB L2 cache.

If you want to upgrade to 2MB, both 64Kx64 SRAM chips must removed and replaced by 128K64 chips and R113 has to be moved to position R112.
In addition R127/R128 and R129/R130 have to be adjusted for the different pinout.
I did not do this here for a reason: For 2MB cache you need a 64Kx8 TAG RAM (32-pin) with 8nS "speed" that offers the additional address lines. The layout of the K6XV3+ is prepared for this but these chips are very very hard to find today.
There are still 128Kx8 chips made today but I never found 8nS ones. If someone has a source for such chips please let me know.

And here´s a picture of the "finished product" (the sticker still says 512K):

K6XV3_2a.JPG
Filename
K6XV3_2a.JPG
File size
819.73 KiB
Views
173 views
File license
Fair use/fair dealing exception
Last edited by majestyk on 2022-12-02, 14:06. Edited 5 times in total.

Reply 1 of 5, by dr_st

User metadata
Rank l33t
Rank
l33t

Very interesting. I would consider doing this to my K6XV3+/66, but I suspect that board has severe aging issues, so at this point I don't feel like investing into a board that may die any day...

https://cloakedthargoid.wordpress.com/ - Random content on hardware, software, games and toys

Reply 2 of 5, by majestyk

User metadata
Rank Oldbie
Rank
Oldbie

Limiting factor are the crappy green electrolytics in the VRM circuitry around the CPU socket. So I would recommend a recap before going any further.

I forgot to mention the cacheable areas:

"Write Through"
512K -> 128MB RAM
1024K -> 256MB RAM
2048K -> 512MB RAM

"Write Back"
512K -> 64MB RAM
1024K -> 128MB RAM
2048K -> 256MB RAM

Reply 3 of 5, by dr_st

User metadata
Rank l33t
Rank
l33t
majestyk wrote on 2022-11-16, 08:47:

Limiting factor are the crappy green electrolytics in the VRM circuitry around the CPU socket. So I would recommend a recap before going any further.

This is most likely what I will do when it starts crashing too frequently.

IIRC, if your installed RAM is larger than the cacheable areas, and you don't have a 2+/3+ CPU (with internal cache), then you will experience performance drops, correct? Can stability suffer as well?

https://cloakedthargoid.wordpress.com/ - Random content on hardware, software, games and toys

Reply 4 of 5, by majestyk

User metadata
Rank Oldbie
Rank
Oldbie

Depending on the OS and it´s memory usage there will be performance drops. Stability will not be affected.

I should also add that if you are using a "K6 plus" CPU onboard (then) L3 cache becomes an issue of lower importance that doesn´t play a major role in performance.

Don´t wait too long with a recap. Fading electrolytics cause higher ripple on the supply voltages and can stress the chips.

Reply 5 of 5, by majestyk

User metadata
Rank Oldbie
Rank
Oldbie

I found one of my old K6BV3+ /66 the other day that was equipped with just one 1MB cache chip.
I always wanted to upgrade to 2MB but some component was always missing.

The first step is to solder a second 64x128K chip in it´s place.

The second step is to adjust the jumpering. R145 has to be moved to position R143 and R 137 (or R138) to position R203.

The third step is replacing the TAG RAM:
On 512K or 1MB versions there is a 256K chip (32Kx8, 28 pin SOJ 300 MIL) while 2MB boards have a 512K chip (64Kx8, 32 pin SOJ 300MIL). All chips are 8nS.
These 512K chips were made bei Utron and one more manufacturer and are virtually non-existent today. You will find datasheets but no seller offering them.
That´s why I chose a 1MB chip (128Kx8) 10nS hoping a good sample of a 10nS type today might be as good/fast as a bad sample of a 8nS type back in 1999.
These chips are still available, but you have to make sure they´re 300MIL SOJ and that they have the old pinout with Vss and Vcc at pins 32/16. Modern chips have these pins in the middle of the package due to advantages at high frequencies.
Of course there´s one unused address line in the 1MB chip (A16). This line needs to be grounded, the system won´t work with this pin open. There´s a ground pad nearby so this is no effort.

TAG_mod.JPG
Filename
TAG_mod.JPG
File size
719.36 KiB
Views
53 views
File license
Public domain

I still have to test this setup to make sure there are no instabilities at 100MHz FSB.

The FIC VA-503+ has 1MB L2 cache and two 512K chips. The TAG RAM is 256K and the layout only provides the 28 landings for this chip.
I have repeatedly read in online boards that there is a "rare 2MB version" of this model. I doubt this ever exixted due to the TAG limitation.

I tested this setup with both 256MB and 512MB RAM:
In the 256MB case all 256MB are being cached in "Write Back" mode, "Write Allocation" gets enabled by BIOS.

If there´s 512MB RAM present, 512Mb are being cached, but BIOS switches to "Write Through" mode to avoid half of the RAM being uncached. Write Allocation is disabled in this case.
Th data from the table of cacheable areas (see above) is correct as we see.

And here´s a picture of the finished product:

k6bv3plus66_total1.JPG
Filename
k6bv3plus66_total1.JPG
File size
1.28 MiB
Views
25 views
File license
Public domain