Curiously enough I had such an issue yesterday when testing a known good mobo (AOpen AP43). I was swapping a SX955 and SX807 DX2 CPUs to test something and in the process I messed up CMOS data - battery was weak and I didn't do a proper load of defaults after I changed it. Which resulted in the on-board L2 getting detected but not used, almost as if it was fake cache. And then one of the SIMM modules stopped making good contact or something.

Point is, I had the SX955 set to WB, the mobo detected it properly (it calls it P24D) and the benchmarks did return numbers correct for WB operation. But the floppy write got trashed. So I returned to BIOS settings again and there was now L1 cache setting enabled, it offered both WB and WT but defaulted to WT for some reason. Once I set it manually to WB the floppy DMA issue was fixed. BTW there was also the option to enable/disable L1 Burst Writes but it does nothing (at the very least it doesn't break anything no matter what is set).

This is one more data point confirming that mobo jumper settings are one thing but the BIOS must properly set the chipset for WB operation - and it might not be fully automatic (or default), merely enabled if the correct chip is detected.

Deunan wrote on 2023-07-19, 09:58:

This is one more data point confirming that mobo jumper settings are one thing but the BIOS must properly set the chipset for WB operation - and it might not be fully automatic (or default), merely enabled if the correct chip is detected.

Thanks for the data point! Can you add the BIOS vendor (Award, AMI, Phonix, Quadtel, MR) and the BIOS date to this thread, please?

AMI 10/10/94, one of those graphics BIOSes that can use a mouse and takes 5s to load. All in all it's not bad, just has some quirks one needs to keep in mind when swapping CPUs.

Deunan wrote on 2023-07-19, 18:45:

AMI 10/10/94, one of those graphics BIOSes that can use a mouse and takes 5s to load. All in all it's not bad, just has some quirks one needs to keep in mind when swapping CPUs.

So this confirms that AMI didn't do it better than Award. According to Jan (aka chkcpu), Award managed to get auto-WB for Intel/AMD CPUs working mid 1995.

AMIBIOS dated 07/25/94 that I have on a different mobo - SIS 85C471 - is even worse, doesn't properly enable L1 WB mode at all. Even though there does seem to be such an option in the BIOS settings. But the correct jumper positions for WB on 486 are unknown, I've figured them all with the help of SIS datasheet but I'm not 100% sure I connected everything right, so it might be an electrical problem after all. But I've also read somewhere that 471 chipset only supports WB on PODP and it takes 496/497 chipset (that I have on the AP43 mobo) to bring that to 486 CPUs as well. I'm not sure what, if any, differences there are between DX4-style and PODP cache coherency protocols.

It also doesn't help that the 471 mobo doesn't have voltage regulator module, and I'm too lazy to build one, so I can only test one particular 486 CPU on it - the SX955. I might look for a newer BIOS anyway since this one is also limited to 1024 cylinders in CHS mode and doesn't do any translation. Problem is the mobo ROM is only 64k (unlike 128k on AP43) and also has graphics UI, so I'm not sure how much more code can be added there.

Deunan wrote on 2023-07-20, 09:57:

But I've also read somewhere that 471 chipset only supports WB on PODP and it takes 496/497 chipset (that I have on the AP43 mobo) to bring that to 486 CPUs as well. I'm not sure what, if any, differences there are between DX4-style and PODP cache coherency protocols.

The only difference between the PODP and the DX4-style cache coherency protocol is the pin position on socket 3. Given jumpers to connect the DX4-style pins to the traces connected to the PODP-style pins, DX4 support is fine on the electrical side. A lot of mainboards from that era lack the required jumpers, though. On the other hand, Cyrix has a WB coherency protocol since the first Cx486DX protocol which is again a completely different pinout and IIRC also slightly incompatible on the electrical level. The Cyrix WB protocol and the DX4 WB protocol use some of the same pins for entirely different functions, and earlier 486 mainboards have those pins hard-wired to the appropriate chipset pins for the Cyrix pinout.

The release dates of the 471 and the 496 make it quite likely that most 471-based mainboards do not have the required jumper for the DX4-style pinout, but most 496-based mainboards do. A correlation thus wouldn't surprise me, but I confident there is no causation. Furthermore, the PODP processors are quite rare. It's also possible that some revisions of the 471 chipset just don't work with the PODP/DX4 protocol at all due to chipset bugs. As long as they work fine with the Cyrix protocol (which was deployed into mass-market systems way before the Intel protocol), most users wouldn't notice.

Deunan wrote on 2023-07-20, 09:57:

It also doesn't help that the 471 mobo doesn't have voltage regulator module, and I'm too lazy to build one, so I can only test one particular 486 CPU on it - the SX955. I might look for a newer BIOS anyway since this one is also limited to 1024 cylinders in CHS mode and doesn't do any translation. Problem is the mobo ROM is only 64k (unlike 128k on AP43) and also has graphics UI, so I'm not sure how much more code can be added there.

Maybe that board also accepts 128K BIOS chips. Maybe later BIOSes dropped the graphical stuff. Some board manufacturers even switched from AMI WinBIOS to Award during the lifetime of a board. A 64K chip doesn't necessarily mean you can't get a newer BIOS with improvements at the relevant things (IDE translation, WB initialization).

mkarcher wrote on 2023-07-20, 10:10:

Some board manufacturers even switched from AMI WinBIOS to Award during the lifetime of a board.

That is exactly what happened, all post-94 BIOSes are AWARD, not AMI. I've collected some but haven't tested any yet. Some of the late '95 BIOSes mention different (higher) mobo revisions - I'm not sure if there are PCB fixes or is there a difference in the chipset. The photos all look to have the same "85C471" main chip but the BIOS strings often mention B, E or G. Datasheet for the '471 doesn't include such info, or I have missed it.

As for jumpers, there's plenty. Numbering goes up to mid-40 and I think the necessary connections for P24D type chip are there, but until (if?) I get it to work properly I can't be 100% sure. But just now I noticed that 471 datasheet mentions something about "Hardware Trap Definition" which is configured by weak pull-up registers on DACK inputs (of all pins). And I think I found some jumpers for this purpose, that I didn't understand, I might need to revisit this.

Deunan wrote on 2023-07-20, 11:28:

The photos all look to have the same "85C471" main chip but the BIOS strings often mention B, E or G. Datasheet for the '471 doesn't include such info, or I have missed it.

That's too bad, but common with those datasheets. For the SiS 496/7, you find copies of the latest revision of the datasheet which includes EDO RAM support, but no mention that this only applies to the latest hardware revision, and how to tell the revisions apart.

Deunan wrote on 2023-07-20, 11:28:

But just now I noticed that 471 datasheet mentions something about "Hardware Trap Definition" which is configured by weak pull-up registers on DACK inputs (of all pins). And I think I found some jumpers for this purpose, that I didn't understand, I might need to revisit this.

That's a slightly unusual term in the data sheet. SiS calls it "trap" when everyone else calls it "strap". These "hardware traps" on the 471 are a BIOS-independent way of configuring the L1WB protocol. For the 471, I don't know whether the L1WB protocol is updatable by the BIOS, or whether these traps / straps are the only way to configure it.

mkarcher wrote on 2023-07-20, 15:11:

For the SiS 496/7, you find copies of the latest revision of the datasheet which includes EDO RAM support, but no mention that this only applies to the latest hardware revision, and how to tell the revisions apart.

Oh, good thing you told me that, I was just about to test some RAM sticks with that mobo since currently it has 4* 4M FPM config and I think 16M is not a good match for Am5x86-133 , I'd rather have 32M but I'm running low on 16M SIMMs so I wanted to try some 8M ones. 4 slots providde some opportunity to get rid of some less useful SIMMs that don't really work well anywhere else (like small capacity EDO).

mkarcher wrote on 2023-07-20, 15:11:

SiS calls it "trap" when everyone else calls it "strap". These "hardware traps" on the 471 are a BIOS-independent way of configuring the L1WB protocol. For the 471, I don't know whether the L1WB protocol is updatable by the BIOS, or whether these traps / straps are the only way to configure it.

Ha, straps, I never made the connection. This makes more sense. The doc says it can be switched via chipset register 0x50, bit 4, and does mention P24D, so I wonder why these straps are needed (or even _if_ they are).

Also, I need to make a correction regarding the BIOS date. While it does say 10/10/94 in the header and the last 16 bytes, the actual date is Feb.27.1996. I forgot I've updated this BIOS before, and both the original and the updated files are internally compressed and carry same '94 dates but when the 0xF000 segment is dumped on a running system such strings can be found:

AMIBIOS W 05 11 10/10/94(C)1994 American Megatrends Inc., All Rights Reserved
(C)1994 American Megatrends Inc.,
41-PG0A-001770-00101111-101094-SIS496AB
000-0-0000-00-00-0000-00-00-000
000-0-0000-00-00-0000-00-00-00-1
AMIBIOS (C)1994 American Megatrends Inc.,
AP4 R1.61.S Feb.27.1996

And sure enough I had updated it to "1.61s" version some years ago. So it's like there's a loader with '94 date and the actual compressed modules are from '96. Well, just because something was fixed in '96 doesn't mean the whole code got updated, as the header shows this probably isn't the case.

Deunan wrote on 2023-07-20, 16:51:

So it's like there's a loader with '94 date and the actual compressed modules are from '96.

Exactly. The usual name for that loader is "boot block", and it usually contains a micro-BIOS that is good enough to run a flash utility from floppy. This micro-BIOS is invoked when the compressed modules seem corrupt.

I think my Acer VI15G (SiS471) sets the L1 WB cache for P24D properly with an AMI WinBIOS from 1994, but it's been a long time so I would need to check again. Award BIOS from 1995 onwards work just fine to set L1 WB on DX4 for SiS471 chipsets assuming the board has the appropriate jumpers (examples: ASUS VL/I-486SV2GX4 or GA-486VS with Jan's modded BIOS, both boards made in '94 with the ASUS having a 471 chip from week 16-1994, so quite early). One thing I've noticed on both of those that the CACHE# line of the CPU is pulled high by a resistor instead of connecting it to the chipset, not sure if it has any impact but the L1 WB is detected and seems to work properly.

Back to AMI, maybe it is just bad luck on my part but I've found AMI BIOSes for SiS471 (both the WinBIOS from '94 and the earlier Hi-Flex from late '93) to be substandard when it comes to performance. On all my 471 boards with AMI, there's always some bug or limitation that prevents me from setting the tightest timings. On all of them either the 'Fastest' DRAM option or the '1T' Cache Burst Read options (or both) are completely ignored, always using 'Fast' and '2T' instead.

mkarcher wrote on 2023-07-17, 21:24:

Award also derives the clock multiplier from Reset_DX. It later measures the processor performance to get the CPU clock and then derives the bus clock for autoconfig by dividing by the clock multiplier. Do you know how Award dealt with the AMD DX4 NV8T (no CPUID support, and the same Reset_DX4 2x in both x2 and x3 mode)? If you detect a no-CPUID DX2-type CPU at 100MHz, it can be an NV8T at either 3x33 or at 2x50.

Detection of the Am486DX4 NV8T in the Award BIOS is indeed done by checking for CPU speed. If Reset_DX indicates an Intel/AMD DX2 CPU and the speed is 90MHz or higher, it must be an Am486DX4 because the fastest DX2 is the Am486DX2-80.
At the same time the x2 multiplier bit is reset and the x3 bit is set so the autoconfig still works. This means the BIOS always assumes an Am486DX4-100 NV8T to run 3x33MHz mode… 😉

I found this Am486DX4 NV8T detection logic already in a November 1994 Award BIOS. But an even earlier July 1994 BIOS didn’t support this CPU and indicated the Am486DX4 as an 80486DX2 CPU at 100MHz.

Jan

Deunan wrote on 2023-07-20, 16:51:

mkarcher wrote on 2023-07-20, 15:11:

SiS calls it "trap" when everyone else calls it "strap". These "hardware traps" on the 471 are a BIOS-independent way of configuring the L1WB protocol. For the 471, I don't know whether the L1WB protocol is updatable by the BIOS, or whether these traps / straps are the only way to configure it.

Ha, straps, I never made the connection. This makes more sense. The doc says it can be switched via chipset register 0x50, bit 4, and does mention P24D, so I wonder why these straps are needed (or even _if_ they are).

Apart from setting SiS471 register 50h bit 4 by the BIOS for L1 cache WB mode, some chipset pins need to change function for the Intel/AMD WB-protocol to work. This is where the 2 hardware trapping jumpers to DACK1* and DACK0* are for. The SiS471 datasheet indicates this setting on page 22.

The Hardware Trap Definition of the DACK1* and DACK0* pins should be as for the P24D/P24T to get the Intel/AMD WB-protocol, so both these pins must be connected to a 2K2 pull-up resistor.
Although only the Intel 486DX2WB (P24D) and POPD (P24T) are mentioned, this setting is also needed for the Intel 486DX4WB, Enhanced Am486DX2, Enhanced Am486DX4, and Am5x86.
As the DACK1* DACK0* hardware trapping has to be set differently for other CPU models, I expect the jumper pins for this to be populated on any SiS471 board. At least they are on my Chicony CH-471B.

The most noticeable function change is about the "CACHE" and "PCD" signals on chipset pin 118.
The SiS471 datasheet says:

So it makes sense to connect CPU “CACHE*” to Chipset “PCD” because this chipset pin 118 changes function to “CACHE*” when both DACKs are pulled high.
I use these jumper settings when running an Am5x86 in L1 WB mode on my SiS471 board;
- CPU “CACHE*” to Chipset “CACHE*” (PCD)
- CPU “HITM*” to Chipset “HITM*”
- CPU “WB/WT*” pulled high
- but I have CPU “INV” unconnected.
It works fine that way, but it may not be set for optimum performance. I need to experiment more on how to connect the INV signal and if connecting it to W/R* works better.

Jan

Chkcpu wrote on 2023-07-21, 17:49:

Apart from setting SiS471 register 50h bit 4 by the BIOS for L1 cache WB mode, some chipset pins need to change function for the Intel/AMD WB-protocol to work. This is where the 2 hardware trapping jumpers to DACK1* and DACK0* are for. The SiS471 datasheet indicates this setting on page 22.

Thanks for the info. I belive I had INV connected properly, and also INIT -> SRESET (this is part of -S extensions but I understand it's not optional with WB since the cache will get invalidated before written back on hard reset). But I didn't touch the strap jumpers, not understaning what they do exactly, and also now that I look at my notes the CACHE signal could be wrong because I just spotted a typo. I will revisit this once I have some more free time.

This is OT but I also noticed this mobo somehow not being happy with SX CPUs - something about NMI. It tends to hang during early mobo init when the chips are cold, this doesn't happen when warm and also doesn't happen when NMI jumper is open, leaving the pin on SX floating. Curiously DX CPUs don't suffer from the same issue, with NMI connected the mobo always boots properly and is stable. Has anyone noticed anything funny with SiS 471 and SX CPUs? If not it could be down to my particular mobo, and the routing of NMI for SX models (since DX works well) - like a cracked via or something of the sort.

Deunan wrote on 2023-07-21, 18:08:

Chkcpu wrote on 2023-07-21, 17:49:

Apart from setting SiS471 register 50h bit 4 by the BIOS for L1 cache WB mode, some chipset pins need to change function for the Intel/AMD WB-protocol to work. This is where the 2 hardware trapping jumpers to DACK1* and DACK0* are for. The SiS471 datasheet indicates this setting on page 22.

Thanks for the info. I belive I had INV connected properly, and also INIT -> SRESET (this is part of -S extensions but I understand it's not optional with WB since the cache will get invalidated before written back on hard reset).

It's not exactly before written back, but instead of written back. Systems seem to work fine even with hard reset for most tasks, because there is no point to cause a CPU reset of a 80486 during normal execution of 386/486 user-space software. There are two reason to cause a CPU reset during system operation: (1) compatibility with 286 software that uses a CPU reset to get the CPU from protected mode back to real mode; (2) resetting the CPU to obtain the CPU ID for CPUs that do not yet implement the CPUID instruction. Whenever one of these use cases is executed with INIT not remapped to SRESET, the new data of dirty L1 cache lines is lost.

INIT -> SRESET increases performance of 286 software that uses CPU reset to switch modes often (maybe some old 286 Windows versions do; later Windows versions like 3.1 use CPU reset to get back to real mode only if no 386-like processor is detected), even if you use L1WT, because a soft reset doesn't invalidate the L1 cache, which saves both the time required for invalidation and it allows hot data to stay in cache across the system reset.

Deunan wrote on 2023-07-21, 18:08:

This is OT but I also noticed this mobo somehow not being happy with SX CPUs - something about NMI. It tends to hang during early mobo init when the chips are cold, this doesn't happen when warm and also doesn't happen when NMI jumper is open, leaving the pin on SX floating.

... and the routing of NMI for SX models (since DX works well) - like a cracked via or something of the sort.

It seems you are aware that NMI requires jumpering. NMI is on A15 on on SX CPUs, but on B15 on DX CPUs. Your issue sounds indeed like a broken trace (or via) from A15 to the NMI jumper. A broken trace can work properly depending on temperature, because thermal expansion can cause the parts of a cracked trace to touch, bridging the break. Also, there still is capacitive coupling over a gap. Logic signals are specified to require DC coupling, but they can work in unexpected ways even if only AC (capacitive) coupling is present. The way it works can depend a lot on the temperature of the receiver chip if it has a pure CMOS input. Ideally, a pure CMOS input has high impedance, and does neither force the input high or low, but in practice, temperature-depedent leakage of the input transistor and more importantly the input protection diodes have an effect on the DC level at a CMOS input that has no proper DC path to Vcc, GND or a logic output. The DC level influences whether the input appears low all the time, high all the time, or somehow reacts to edges on the signal.

Chkcpu wrote on 2023-07-21, 15:01:

Detection of the Am486DX4 NV8T in the Award BIOS is indeed done by checking for CPU speed. If Reset_DX indicates an Intel/AMD DX […]
Show full quote

Detection of the Am486DX4 NV8T in the Award BIOS is indeed done by checking for CPU speed. If Reset_DX indicates an Intel/AMD DX2 CPU and the speed is 90MHz or higher, it must be an Am486DX4 because the fastest DX2 is the Am486DX2-80.
At the same time the x2 multiplier bit is reset and the x3 bit is set so the autoconfig still works. This means the BIOS always assumes an Am486DX4-100 NV8T to run 3x33MHz mode… 😉

I found this Am486DX4 NV8T detection logic already in a November 1994 Award BIOS. But an even earlier July 1994 BIOS didn’t support this CPU and indicated the Am486DX4 as an 80486DX2 CPU at 100MHz.

Jan

Hopefully it won't get confused by a DX2-80 to overclocked 50x2 or an NV8T DX4-100 running at 50x2 too.
I remember mkarcher playing with his DX4-120 @ 60x2 MHz, but luckily that was a SV8B with CPUID support.

Disruptor wrote on 2023-07-22, 12:14:

Hopefully it won't get confused by a DX2-80 to overclocked 50x2 or an NV8T DX4-100 running at 50x2 too.

Of course these cases will be mishandled. But on many BIOSes, this has an effect on auto-configuration only. For general use, 3*33MHz is recommended over 2*50MHz, because you have much higher margin at FSB33 than at FSB50, unless you insert an amount waitstates that makes FSB50 worse than FSB33 without those waitstates. If you are hunting the last bits of performance, you likely disable auto-config anyway.

One exception I am aware of: The UMC8881 has a programmable PCI clock divider. The AWARD BIOS for this chipset executes the POST with a PCI clock divider depending on the FSB clock determined by CPU_CLOCK/CPU_Multiplier. At FSB40 and FSB50, you get PCI=FSB/2, at FSB33 and lower, you get PCI=FSB. With a 2*50 DX2 (or an NV8T DX4 in x2 mode), the BIOS will errorneously assume FSB33 instead of FSB50 and configure 1:1 fraction, overclocking the PCI bus to 50MHz during POST. The CMOS setup setting for the divider (unless this option is hidden) is applied after the POST has finished.

Baoran wrote on 2023-07-12, 16:00:

Exp4045 motherboard thinks it is a 120Mhz am486dx4-S during post when in 4x mode and 100Mhz am486dx-s when it is in 3x mode. Changing multiplier does not make any difference when it comes to problems. Only thing that makes floppy and turbo button work normally is removing JP16 that changes what CHKCPU reports from Write back to Write through and makes the system slower too showing in speedsys score that I mentioned earlier.

Hi Baoran,

I’ve completed the disassembly and analysis of your EXP4045 v2.3 BIOS and found automatic L1 cache WB enable logic for any WB capable Intel and AMD CPU, except the Am5x86 in x4 mode.
So the L1 cache in WB mode should have worked with the Am5x86 in x3 mode, provided the CPU is good, the jumper settings are correct, and the chipset revision on this board supports L1 WB.
Indeed a lot of uncertainties.

To isolate the root cause, do you have any other WB capable Intel or AMD CPU to test with?
If not, can you tell us the CPU Type Configuration jumper settings you used for the Am5x86 in x4 and WB mode? Or show us a picture of the board with these settings?

I can patch the EXP4045 v2.3 BIOS for proper Am5x86 and x4 multiplier support, but without knowing the cause of the L1 WB issue I don’t expect a patched BIOS will fix your WB issue either…

Another avenue is to try to get the Am5x86 working correctly in WB mode on the LS-486E Rev D board, so we know the CPU is good.
To help you here, please tell us the BIOS version and jumper settings you used on this PCI board. Also the indications about CPU type and speed on the BIOS boot screens, in both WT and WB mode, will help.

Regards, Jan

Chkcpu wrote on 2023-07-23, 12:02:

Hi Baoran, […]
Show full quote

Baoran wrote on 2023-07-12, 16:00:

Exp4045 motherboard thinks it is a 120Mhz am486dx4-S during post when in 4x mode and 100Mhz am486dx-s when it is in 3x mode. Changing multiplier does not make any difference when it comes to problems. Only thing that makes floppy and turbo button work normally is removing JP16 that changes what CHKCPU reports from Write back to Write through and makes the system slower too showing in speedsys score that I mentioned earlier.

Hi Baoran,

I’ve completed the disassembly and analysis of your EXP4045 v2.3 BIOS and found automatic L1 cache WB enable logic for any WB capable Intel and AMD CPU, except the Am5x86 in x4 mode.
So the L1 cache in WB mode should have worked with the Am5x86 in x3 mode, provided the CPU is good, the jumper settings are correct, and the chipset revision on this board supports L1 WB.
Indeed a lot of uncertainties.

To isolate the root cause, do you have any other WB capable Intel or AMD CPU to test with?
If not, can you tell us the CPU Type Configuration jumper settings you used for the Am5x86 in x4 and WB mode? Or show us a picture of the board with these settings?

I can patch the EXP4045 v2.3 BIOS for proper Am5x86 and x4 multiplier support, but without knowing the cause of the L1 WB issue I don’t expect a patched BIOS will fix your WB issue either…

Another avenue is to try to get the Am5x86 working correctly in WB mode on the LS-486E Rev D board, so we know the CPU is good.
To help you here, please tell us the BIOS version and jumper settings you used on this PCI board. Also the indications about CPU type and speed on the BIOS boot screens, in both WT and WB mode, will help.

Regards, Jan

Unfortunately all my other 486 cpus are 5V ones without WB support

Cpu looks exactly same as in the picture of 5x86 wiki page https://en.wikipedia.org/wiki/Am5x86 and even the number 25544 is the same at the bottom. Jumpers are set exactly like for 80486dx4 based on https://theretroweb.com/motherboard/manual/32985.pdf jumper manual except JP16 that controls the multiplier needs to be set to similar to 2x in the table in that pdf to get 4x multiplier while removing that jumper makes it 3x and removing jumper JP32 causes it to go WT mode and makes the turbo button and floppy drive work properly again.

Next step probably is to try finding another cpu to test the motherboards with so I can rule out any problems with the cpu itself. I will also dig up the LS-486E motherboard again and do more tests with again but if I remember correctly I did use 5x86-P75 jumper settings from the manual download/file.php?id=168270&mode=view JP

I'll also try to see if I can take some pictures too.

Baoran wrote on 2023-07-23, 13:48:

Jumpers are set exactly like for 80486dx4 based on https://theretroweb.com/motherboard/manual/32985.pdf jumper manual except JP16 that controls the multiplier needs to be set to similar to 2x in the table in that pdf to get 4x multiplier.

Right, this may be the problem. The 80486DX4 jumper settings for the EXP4045 don’t support L1 cache WB mode!
The iDX4 is basically a L1 Cache WT only CPU. Okay, Intel later made a WB Enhanced DX4 version, but the jumpers for that model are not in this manual.

A way out of this jumper hell is this nice resource:
http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm
In the table below the socket diagram, you can see that (except for the P24T) all WB capable 486 CPUs from Intel and AMD use the same pins for the essential L1 WB signals INV (A10), HITM (A12), CACHE (B12), and WB/WT (B13).

The jumper settings for iDX4-WB, Am486DX2-WB, Am486DX4-WB, and Am5x86 are not in the manual. But luckily the settings for the P24D (i486DX2-WB) are, so you can use those for the Am5x86!

The only deviation of course is to keep the CPU Voltage selection on 3.3V!! 😉

Without the JP16 7-8 jumper, the Am5x86 should now run correctly in x3 multiplier and L1 cache WB mode with the v2.3 BIOS. I really hope this works!

Jan