Reply 20 of 60, by Deunan
Curiously enough I had such an issue yesterday when testing a known good mobo (AOpen AP43). I was swapping a SX955 and SX807 DX2 CPUs to test something and in the process I messed up CMOS data - battery was weak and I didn't do a proper load of defaults after I changed it. Which resulted in the on-board L2 getting detected but not used, almost as if it was fake cache. And then one of the SIMM modules stopped making good contact or something.
Point is, I had the SX955 set to WB, the mobo detected it properly (it calls it P24D) and the benchmarks did return numbers correct for WB operation. But the floppy write got trashed. So I returned to BIOS settings again and there was now L1 cache setting enabled, it offered both WB and WT but defaulted to WT for some reason. Once I set it manually to WB the floppy DMA issue was fixed. BTW there was also the option to enable/disable L1 Burst Writes but it does nothing (at the very least it doesn't break anything no matter what is set).
This is one more data point confirming that mobo jumper settings are one thing but the BIOS must properly set the chipset for WB operation - and it might not be fully automatic (or default), merely enabled if the correct chip is detected.