jakethompson1 wrote on 2024-03-03, 01:43:Is it fair to say that the MWDMA feature of ATA didn't get much exercise prior to the Triton chipset?
That sounds correct, yes.
rasz_pl wrote on 2024-03-03, 01:52:At least for few 486 motherboard diagrams I have (for example http://www.bitsavers.org/pdf/samsung/pc/98134 … Manual_1993.pdf) ISA address bus is directly connected to L2 cache. This means CPU must be HOLD/AHOLDed during ISA DMA. Intel Pentium chipsets keep ISA behind PIIX PCI-ISA bridge so those platforms should be able to run unfazed by ISA DMA.
Thanks for the link. The diagrams are interesting and some stuff looks different than what I am used to. For example, as you say, the cache address lines are connected to the ISA side of the address bus, which is buffered by LS-series (not even F-series) logic chips. Only the tag RAM is connected directly to the front-side bus. The "low" cache address line CA4-CA9 are split from SA4-SA9 only because SA4-SA9 can be driven by the ISA refresh controller. As the first cycle of a burst takes 2 clocks at least, the LS chips might be fast enough, though. In my experience, on late 486 mainboards it is more common to have the complete cache address bus driven directly from the CPU address bus, possibly with F244 drivers in between.
Furthermore, I am surprised by the IRQ signal conditioning circuit. It can enforce a minimum low pulse width (if I understand it correctly) on IRQ5 or IRQ9 and on IRQ10 or IRQ11. Why would anyone want to re-shape just two IRQ lines, and make them selectable?
Having the CPU in AHOLD all the time during ISA DMA transfer makes sense, because it's the easiest way. Provide address bits all the time and just apply EADS whenever a transfer happens.
rasz_pl wrote on 2024-03-03, 01:52:Why do I remember ISA sound cards measurably slower than PCI ones back in the day? Is this another false memory of mine? 😀 I remember articles advising to upgrade to gain fps.
ISA DMA surely puts a lot of load on the ISA bus - even when the ISA bus is separated from the PCI/memory bus. The worst thing you can do is to use an 8-bit DMA channel (like WSS does) to transfer 16-bit stereo data, and configure the DMA controller to "single mode" which causes the DMA controller to re-arbitrate for the ISA bus every single byte. WSS-type cards work perfectly fine in "demand mode", in which the chip can re-fill its internal FIFO in a "burst" in which the ISA DMA controller keeps ownership of the bus. Anything competing on the ISA bus gets slowed down by sound card DMA. A usual ISA/PCI bridge should contain an 8 byte or 16 byte ISA DMA read-ahead/write-post buffer, reducing the number of times it needs to arbitrate for the PCI bus, but it is likely that some PCI sound cards have bigger FIFOs than that and don't need to take PCI bus ownership that often as the ISA bridge needs.
If you have an ISA VGA card, the drawing performance is significantly affected by ISA DMA competing for the ISA bus, but if you use an ISA VGA card in a system that could host a PCI sound card, you have more serious performance issues than just the sound card DMA hogging the ISA bus. I'm wondering what other ISA resources could be used by a game that will be a performance bottleneck in presence of ISA DMA. Game port polling is a terrible thing anyway, and the time required to do it does not depend on bus load, but on the joystick position. OPL2 "delay loops" reading the status port 20 times are definitely affected by ISA DMA and slowed down considerably, but I don't expect games to perform that much OPL2/OPL3 writes that it should cause serious performance issues. Another idea would be ISA palette snooping if the game is performing a lot of color reprogramming effects.
Ran into this curiosity:
https://www.lo-tech.co.uk/wiki/XT-CFv3
General Description
The XT-CFv3 is a bootable 8-bit ISA to CompactFlash adapter for XT and AT class IBM compatible PCs.
Replace dead MFM or RLL hard disks with cheap CompactFlash or Microdrive media
Easy to access CompactFlash card (without opening the PC)
Reduce system power consumption (and hence load on the PSU) by as much as 30W
Uses the XT-IDE Universal BIOS (adapter type is 'lo-tech XT-CF')
32K in-system re-programmable ROM (with 24K free for any other ROM code)
Can be used in IBM Personal Computer XT System Board Slot 8
Reduced wait-state operation in PC/AT and newer hardware
High-speed DMA operation; up to 500KB/s in a 4.77MHz PC/XT
......
ISA B8 and DMA Function
The purpose of the ISA B8 signal depends on the system architecture:
For the PC/XT, B8 is as a card select line to read from a card physically in the ISA slot closest to the CPU (known as slot 8 ), and has no function in other slots.
In PC/AT and above, B8 is instead used to reduce wait-states.
Since the design of the PC/XT system board prevents DMA transfers from slot 8, slot 8 and DMA are mutually exclusive.
For the XT-CFv3 card to co-exist in a system with an MFM controller or other device that requires DMA Channel 3, DMA must be disabled by setting switch 4 ON.
douglar wrote on 2024-04-01, 20:05:
I remember reading blog post accompanying this, here it is https://www.lo-tech.co.uk/xt-cfv3-dma-transfer-mode/
beneficial in stock XT where it would reliably hit 500KB/s versus ~300KB/s with V30, those results are there at the bottom https://www.lo-tech.co.uk/wiki/XT-CFv3#Performance 😀 once you move to 286 or 16bit ISA it no longer makes sense to use ISA DMA 🙁
We are not talking about Windows 3.1 anymore (thread subject), but that's ok.
I use the assembled version of these 8-bit XT-IDE controllers from TexElec.
More specifically the Lo-tech XT-CF-lite rev.2 one. Highly recommend. Simplifies the whole XT-IDE setup. The compact package with CF slot is a plus.
However they are good fit for XT class hardware only. Too slow for 286 and later machines.
My understanding is that DMA makes sense for standard XT system running at 4.77MHz.
For anything faster than that Intel's 8237 becomes the limiting factor.
Can somebody disprove that ?
On 16-bit ISA bus, the bus-mastering Adaptec AHA-1542 outperforms standard IDE controllers.
Same applies to bus-mastering VLB SCSI controllers compared to VLB IDE ones.
Finally, non-bus-mastering EIDE VBL controllers are much faster than bus-mastering VLB SCSI ones.
It is not clear to me how much DMA is a factor vs the wider SCSI/EIDE designs.
Any opinion on this ?
pshipkov wrote on 2024-04-02, 15:25:Same applies to bus-mastering VLB SCSI controllers compared to VLB IDE ones.
Finally, non-bus-mastering EIDE VBL controllers are much faster than bus-mastering VLB SCSI ones.
It is not clear to me how much DMA is a factor vs the wider SCSI/EIDE designs.
How widespread was bus mastering on VLB? I seem to remember some motherboards just not bothering to support bus mastering on VLB in the first place.
I dont remember ever seeing bus mastering VLB IDE controller 🙁
rasz_pl wrote on 2024-04-03, 06:55:pshipkov wrote on 2024-04-02, 15:25:Same applies to bus-mastering VLB SCSI controllers compared to VLB IDE ones.
Finally, non-bus-mastering EIDE VBL controllers are much faster than bus-mastering VLB SCSI ones.
It is not clear to me how much DMA is a factor vs the wider SCSI/EIDE designs.How widespread was bus mastering on VLB? I seem to remember some motherboards just not bothering to support bus mastering on VLB in the first place.
I dont remember ever seeing bus mastering VLB IDE controller 🙁
Just a guess here, but since we are talking about the 386/486 CPU bus that was not designed with expansion cards in mind, I'd strongly suspect that all VLB bus mastering would have to be "first party" bus mastering, where all the bus master circuitry is on the VLB card. I wouldn't expect any third party bus master on the motherboard or in the CPU chipset.
I've got a buslogic/tekram caching IDE controller that moves data at 20MB/s from the cache with a 33Mhz bus speed. I assumed it was doing some sort of bus mastering to hit those speeds. Not sure how to verify that.
Picture and BIOS here: http://vogonsdrivers.com/getfile.php?fileid=2154
douglar wrote on 2024-04-03, 14:01:Just a guess here, but since we are talking about the 386/486 CPU bus that was not designed with expansion cards in mind, I'd strongly suspect that all VLB bus mastering would have to be "first party" bus mastering, where all the bus master circuitry is on the VLB card. I wouldn't expect any third party bus master on the motherboard or in the CPU chipset.
Yes, thats a given. I mean I saw boards with annotation next to VLB slot saying something like "no bus master capable".
douglar wrote on 2024-04-03, 14:01:I've got a buslogic/tekram caching IDE controller that moves data at 20MB/s from the cache with a 33Mhz bus speed. I assumed it was doing some sort of bus mastering to hit those speeds. Not sure how to verify that.
set lowest multiplier and disable L1 cpu cache maybe to exclude cpu factoring in?
VLB SCSI controllers bus-master.
VLB IDE/EIDE don't.
Litmus test:
Use CPU with WB L1 cache. Enable it through BIOS and/or motherboard jumpers.
Bus-mastering controller will hang the system during POST or BOOT.
Hmm lack of handling cache coherency would certainly do it. Maybe thats the reason for those warnings I saw.
rasz_pl wrote on 2024-04-03, 22:45:Hmm lack of handling cache coherency would certainly do it. Maybe thats the reason for those warnings I saw.
Actually, there are control lines on the VLB to handle cache coherence. Some versions of the Adaptec 2842 bus mastering SCSI controller have a jumper to interrupt this line, to support incompatible mainboards, when L1WB is not used. Any VLB master device that accesses memory space needs to support the cache coherence protocol to be compatible with L1WB. It works by probing the cache using LEADS (pin A58) and listening for a "stop, I need to flush that dirty L1 line first" signal on WBACK (pin A38). The latter signal is interrupted by the "write-back jumper" on the 2842.
Good note.
Also, can you point us to such implementation ?
Haven't seen one so far, but haven't look for such thing really.
Will be very interesting to experiment with it.
pshipkov wrote on 2024-04-04, 18:46:Also, can you point us to such implementation ?
Haven't seen one so far, but haven't look for such thing really.
Will be very interesting to experiment with it.
I already mentioned a VLB bus master card that tries it best to be L1WB compatible - the AHA-2842VL, at least in later PCB/PAL revisions with that WB jumper. As the AHA-2842A is the successor of the AHA-2842VL, I expect that card to handle L1WB as well.
On the mainboard side, there is no real complication in supporting L1WB signalling on the VL bus, it's just about hooking up some chipset pins (EADS, WBACK aka HITM) to the VL bus if I understand it correctly. Most late VL-only boards are fully master capable in at least two of the VL slots. If I were to build a L1WB VL bus master system, I would likely start with a SiS471 based board. VL mastering is usually not supported on PCI-capable latest-gen 486 boards (SiS 496 / UMC 8881).
i am looking again at the controller here and there is no such jumper or switch.
documentation says nothing too.
AHA-2840/42A never worked with L1 WB on any motherboard.
thats why asking if you are talking about particular card model that is not the standard A.
same applies to VL as well.
thanks.
pshipkov wrote on 2024-04-04, 20:41:i am looking again at the controller here and there is no such jumper or switch. documentation says nothing too. AHA-2840/42A ne […]
i am looking again at the controller here and there is no such jumper or switch.
documentation says nothing too.
AHA-2840/42A never worked with L1 WB on any motherboard.
thats why asking if you are talking about particular card model that is not the standard A.
same applies to VL as well.
thanks.
This thread VLB SCSI Woes (potentially damaged?)- Dell 486 w/ AHA-2842VL has a high-res PCB photo of an AHA-2842VL. While J5 near the VL slot is not populated on that card, my copy of the card does have that jumper populated. IIRC the FAQ by Adaptec says: If you don't use L1WB, pull the jumper in case of trouble. If you do use L1WB, do not pull the jumper. If the system does not work with L1WB and the jumper installed, disable L1WB.
Your comment reminded me of a conversation with PC-Engineer here.
Just read my response to his advise to close J5, then looked at other notes i have and indeed - AHA-2840/42A does work with L1 in WB mode.
Not sure why it was stuck in my head as a no-no. Should have done the background check than speak from memory. Good refresher here. Thanks.
rasz_pl wrote on 2024-02-27, 23:43:ISA DMA, very slow and problematic https://www.os2museum.com/wp/the-danger-of-datasheets/ https://www.os2museum.com/wp/more-fun-with-isa-dma/
Afaik after long search "GSI, INC. MODEL 4C INTELLIGENT IDEA" might be the only IDE controller using legacy ISA DMA https://forum.vcfed.org/index.php?threads/was … 02/#post-527616 but even this one is unconfirmed as nobody was able to get his hands on one, its all speculation based on available jumper description https://arvutimuuseum.ee/th99/c/E-H/20413.htm
I found an advertising flier in the back on an old box!
