Reply 160 of 163, by superfury
So, interrupts are handled like in edge-triggered mode, but the IR lines are treated like parallel lines. Raising a parallel line sets the IRR bit of said lines itself(thus setting the bit in the IRR register). Lowering a line clears the line's IRR bit. Only when all IRR shared lines of an IR line are lowered is the IRR main register bit cleared(keeps getting set while any shared line is still raised and not lowered again by the connected hardware). So in essence, the IRR register functions as an OR-gate that's giving the value of all it's IR lines' raised-and-not-lowered status(0 when all are lowered) using two shadow registers:
- IRR is the status of interrupt requests.
- IRR2 is the parallel lines' actual high/low status(changed by IR hardware).
- IRR3 gets set for a parallel line(IRR2) with raising edge. Lowering edge clears IRR3's line status(combination of edge and level-triggering logic). IRR is set when any IRR3 parallel for said IR is set. The IRR line is cleared when no IRR3 is set.
This results in combined logic supporting both edge-triggered signals(normal PC hardware IR lines) and level-triggered hardware(shared IR lines for IR2(XT-only), IR5 and IR9(AT+).