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Compaq Deskpro 386 CPU emulation issues?

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Reply 160 of 163, by superfury

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So, interrupts are handled like in edge-triggered mode, but the IR lines are treated like parallel lines. Raising a parallel line sets the IRR bit of said lines itself(thus setting the bit in the IRR register). Lowering a line clears the line's IRR bit. Only when all IRR shared lines of an IR line are lowered is the IRR main register bit cleared(keeps getting set while any shared line is still raised and not lowered again by the connected hardware). So in essence, the IRR register functions as an OR-gate that's giving the value of all it's IR lines' raised-and-not-lowered status(0 when all are lowered) using two shadow registers:
- IRR is the status of interrupt requests.
- IRR2 is the parallel lines' actual high/low status(changed by IR hardware).
- IRR3 gets set for a parallel line(IRR2) with raising edge. Lowering edge clears IRR3's line status(combination of edge and level-triggering logic). IRR is set when any IRR3 parallel for said IR is set. The IRR line is cleared when no IRR3 is set.

This results in combined logic supporting both edge-triggered signals(normal PC hardware IR lines) and level-triggered hardware(shared IR lines for IR2(XT-only), IR5 and IR9(AT+).

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Reply 161 of 163, by superfury

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Just optimized the debugger to have a bit more performance: strings containing the actual instruction(without prefixes) are now only set once(except during #UD exceptions, which add a #UD prefix to it). That should minimize the instruction disassembly for the used instruction phases(different phases like read,modify,write), especially in cycle-accurate mode(which has multiple stages most of the time). Thus reducing it to only once for each multi-phased instruction, instead of phase count times(e.g. 3 times for read/modify/write).

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Reply 162 of 163, by superfury

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Just fixed a bug in the UART emulation, where, when having both something to send and receive, and alternating sending and receiving each cycle, ending with prioritized for sending nothing, retry it as a receive instead(preventing disabling of the receiver until something is sent again).

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Reply 163 of 163, by superfury

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Even with the latest improvements and bugfixes, (cwsdpmi and) the i386_nofpu qemu testsuite still triple fault and reset the machine?

It happens when starting the executable?

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