Marco wrote on 2022-10-12, 18:44:
I might be mistaken but I think you mixed some things.
Loading bios default stands for loading standard settings. Loading power on defaults for safe settings. I double checked this in the amisetup. There it is written exactly as I stated with safe settings and standard settings. It’s just a bunch of bios settings.
You are not mistaken, but I think I did not confuse anything, too. Let me explain the process in detail:
- When you turn on the computer, the chipset starts with the values explained in the data sheet. Some of them are adjustable by external resistors.
- Quite early in the power-on process, at the time the POST code 13 is sent to port 80, the BIOS overwrites the datasheet / strap values with the power-on defaults. No matter what's in the CMOS.
- Then the complete POST runs with the safe slow settings from the power-on default.
- At the end of the POST, at POST code 8C hex, the BIOS loads the values that are currently stored in the CMOS setup into the chipset.
- Finally, booting from floppy/hard disk is started.
There are power-on and BIOS defaults for all the hidden options as well as the visible options of the setup. Whenever you load default values in the CMOS setup, even the hidden options are reset to the default value. For fclkdiv, the BIOS default and the power-on default differ. So after you loaded power-on default, the hidden, unchangeable (without AMISETUP) option for fclkdiv is different than after you loaded BIOS defaults.
Marco wrote on 2022-10-12, 18:44:Anyway I tried the following: […]
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Anyway I tried the following:
1. Post - bios - loading power on default.
- system very slow nu si 14,7
- looked in amisetup whether other divider options are there: no
- removed ext osc: system wouldn’t even boot but 9 beeps
Wow, that's actually interesting insight. 9 beeps is "BIOS ROM checksum error", issued at POST code 06, so before the power-on defaults are loaded. As I am very confident that the BIOS ROM checksum isn't actually bad, this seems to indicate that the BIOS ROM is accessed too fast due to the higher ISA clock. As fclkdiv defaults to /6, you should be safe if the fast divider is chosen (50MHz / 6 is around 8MHz). So it seems like your system tries to verify the BIOS checksum at sclkdiv (did you ground extosc output: if yes: this forces sclkdiv!). If pulldowns are installed on the two pins configuring SCLKDIV, sclkdiv is initialized as /2, and trying to read the BIOS at 25MHz is going to fail.