mkarcher wrote on 2022-12-17, 08:40:
As I understand it, you don't (typically) pair a 386DX with a 387SX, but either (old way) with a 287 / 287XL or (new way) a 387 / 387DX. If a 386DX is paired with a 287, the ET bit is set for 16-bit data path. If a 386DX is paired with a 3878, the ET bit is set for a 32-bit data path. On the 386DX, this bit is only about the data path between processor and coprocessor, that's why it is called "extension type". If I understand you correctly, you are currently displaying a 386DX + 287 (ET set to 16-bit data path) as 386SX + 387SX. On the 386SX, the ET bit is documented to be fixed at 1. The 386DX datasheet I have at hand describes this bit as "reserved, do not modify". According to Intel the processor should automatically detect at RESET whether a 387 is present (setting ET=0) or not (287 or no coprocessor, setting ET=1) by samping the ERROR# line after reset. IBM did not wire the ERROR# signal from the FPU to the CPU as Intel intended, but (starting at the AT) routed the FPU error through the PIC, so this "auto-detection" is inoperative in PC-like systems, requiring the BIOS to manually set ET in CR0.
@mkarcher, thanks for providing another piece of the puzzle about this ET bit in CR0.
I have information from various sources that the ET bit can be used for detecting if a 386 CPU is a 386SX or 386DX, and I understand now better why.
So, on the 386SX the ET bit is fixed because this CPU has a fixed 16-bit data path and can only be paired with an FPU that uses the same databus width (387SX). The nice thing is that the 386SX’s ET bit remains fixed, even if an FPU is not installed.
The 386DX on the other hand needs the ET bit to be changeable to indicate if an FPU with 16-bit or 32-bit data path is connected. I was missing that insight, thank you.
One internet source remarked that later 386DX models couldn’t cooperate with 16-bit FPUs (287) anymore, but that for compatibility reasons the ET bit can be set on any 386-like CPU with a 32-bit bus, but not on those with a 16-bit bus.
Various code samples I’ve seen just try if the ET bit can be toggled, instead of reading its ‘1’ or ‘0’ state. And this is what CHKCPU does as well on 386 systems, to see if it is dealing with a 386SX or 386DX CPU.
So when I spoke about using the ET bit for 386SX/DX detection, I meant “trying if this bit can be changed”.
CuPid (author of CPU-Z) told me a while back that this 16/32-bit buswidth detection works on both Intel and AMD 386s, as well as the 386 upgrade CPUs Cx/TI486SLC/DLC, IBM 486SLC/SLC2 (not tested yet on an IBM 486DLC2/BL2/BL3), and supposedly on Ti486SXLC/SXL (confirmed now, tested by feipoa).
I’m confident it works on the IBM Blue Lightning as well and CHKCPU is using this ET bit toggle logic on all these 386 (upgrade) CPUs to be more accurate in its CPU type display.
Now, for detecting a 287 or 387 FPU, I use the +infinity/-infinity test. On the first-generation 80287 these values were the same, but on 287XL/387 and comparable FPUs, sporting full IEEE 754 compatibility, +infinity is not same as -infinity.
This test makes CHKCPUs FPU indication independed from the 16-bit/32-bit buswidth detection.
Note that I only perform the infinity test when a 80286 or later CPU is detected, because I don’t know how an 8087 or 80187 would react on this test.
To finally answer your question, when an original 80386 or 386DX is paired with a first-generation 287, CHKCPU displays “386DX with 287 FPU”. But when a 287XL or 387 is fitted, CHKCPU displays “386DX with 387 FPU”, while on a 386SX with FPU you will see “386SX with 387SX FPU”.
Jan