Reply 20 of 29, by bananaboy
superfury wrote on 2023-01-02, 12:28:Past active display doesn't toggle display enable. So when it reaches horizontal retrace of vertical display end, it doesn't fli […]
Past active display doesn't toggle display enable. So when it reaches horizontal retrace of vertical display end, it doesn't flip back until the next frame starts with horizontal&vertical counters reset and horizontal display skew clocks after that.
So with 640x400 active display, what software sees:
1. 400 times horixontal retrace. The 400th 'retrace' gets stuck a long time.
2. During that long time being stuck, vertical retrace flips on and off (usually, can happen anytime though).
3. Bit 0 clears and a new frame is rendering at horizontal display skew.
4. Back to step 1.
Thanks for the reply! I don't think that's correct that the horizontal retrace gets stuck a long time, at least on the VGA. I've attached a test program which is the exact code the IBM VGA BIOS uses to count the scanlines (I've written it using Open Watcom 2.0 but it should work in other compilers with minimal changes). You'll see that it counts 400 active display scanlines. If the horizontal retrace got stuck, you would see the "extra scanlines" value would not match "active scanlines" (it's always one more than active scanlines due to the loop counting one more when vertical retrace is detected).
I think I understand why counting up to the vertical retrace works now, however. I had initially assumed that it would also count the bottom overscan and blanking areas which occur before vertical sync. But it looks like during overscan and blanking, the DD bit is never set, and I'm assuming it's because the "display enable" signal is on for that duration. Then when it hits the vertical retrace start time, DD is set (and "display enable" signal is low).
Here's a very interesting thing though. The text you quoted (which looks like it's from the FreeVGA docs but the official IBM VGA/XGA Technical Reference has basically the same) mentions that the bit is the "real-time status of the inverted 'display enable' signal". I did some digging through the CGA circuit diagram (available in the official IBM CGA pdf manual). Indeed, bit 0 is driven directly by the display enable pin on the 6845 (via a NOT gate). Also the VSYNC pin on the 6845 drives bit 3 (although via a latch). If you look at the timing diagram for the 6845 attached (DISPTMG is the DE pin), notice that the DISPTMG signal goes low when Nvd (end of the active display) is hit! There's an overscan area between Nvd and Nvsp (Nvsp is the vertical sync position). The 6845 calls that entire duration "vertical retrace period" and the DE (DISPTMG) signal is low for that entire time, so on CGA it seems like what you said would be correct!
Cheers,
Sam