Reply 20 of 45, by Jollyroger
mkarcher wrote on 2024-01-12, 07:26:About the chip labelling: KM44C1000B is the generic name, KM44C1000BJ is the specific name for that very chip in a SOJ 26/20 pac […]
rasz_pl wrote on 2024-01-12, 02:54:KMM5362000BG build using KM44C1000B http://rfelektronik.se/manuals/Datasheets/KM4 … miconductor.pdf https://datasheetspdf.com/da […]
KMM5362000BG build using KM44C1000B http://rfelektronik.se/manuals/Datasheets/KM4 … miconductor.pdf
https://datasheetspdf.com/datasheet/KMM5362000B2G.html two banks? 4 RAS lines.KMM5362003BG build using KM44C1000BJ, cant locate datasheet
https://datasheetspdf.com/pdf/542921/SamsungE … s/KMM5362003G/1 one bank? two RAS lines (RAS0 and RAS2).Different internal organization.
About the chip labelling: KM44C1000B is the generic name, KM44C1000BJ is the specific name for that very chip in a SOJ 26/20 package. There should be no difference in data memory chips. The main difference is that the 2003 module has a single merged parity chip KM44C1003B (no datasheet found) instead of four dedicated single-bit parity chips
Both modules are two banks: The second module uses /RAS2 and RAS3, not RAS0 and RAS2. PS/2 SIMMs have two /RAS lines per bank: /RAS0 and /RAS2 for the primary bank and /RAS1 and /RAS3 for the secondary bank. The reason for two /RAS line is mainly to split the load of driving up to 36 x1 chips. The older modules has 12 chips per bank (8 data chips (4 MBit: 1M x 4), 4 parity chips (1 MBit: 1M x 1), as already mentioned in the thread), whereas the newer module just has 9 chips per bank: 8 data chips in the same way, but only one 4MBit parity chip in a special "one /CAS per bit" configuration. This special parity configuration can cut costs and behaves the same as the 4 individual parity chips in usual circumstances.
A standard PS/2 SIMM memory controller always drives /RAS0 and /RAS2 to the same level, the same is true for /RAS1 and /RAS3. So as long as the drivers are not overloaded, the memory controller doesn't notice which RAM chips are connected to what /RAS line. Having only 9 chips per module allows a single /RAS line to be used without being afraid of overloading a standard PS/2 SIMM mainboard. The incompatibility of the newer SIMM may be rooted in different causes: Possibly this system has weaker drivers and can tolerate 6 chips per /RAS line, but not 9 chips per /RAS line. Another (remote?) possiblity is that this board (didn't look into the technology) tries to use the module as four banks of 16 bits by considering /RAS0 and /RAS2 as /RAS lines for dedicated halves of the first bank. This will work only if the routing of the /RAS lines to the memory chips is split exactly in the way the main board expects - and it will not work at all with the "merged parity chip" design of the later module, because splitting the bank into two x18 halves requires two parity chips connected to /RAS0 and the other two parity chips connected to /RAS2.
Understood, very interesting!
Is there any way to analyze any of this with a scope? Perhaps looking at the RAS lines and accessing the RAM at alternate word addresses?