rasteri wrote on 2024-04-01, 18:05:IIRC there's a register to switch LDRQ1 between a GPIO pin and LDRQ. I'll have a look through the manual. […]
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LSS10999 wrote on 2024-04-01, 15:04:
Disabling the onboard audio allowed me to set IRQ7 for the sound card. However, it seems LDRQ1# I brought out is not working correctly, as DIAGNOSE currently gets stuck at DMA section, saying the DMA channels are not usable.
IIRC there's a register to switch LDRQ1 between a GPIO pin and LDRQ. I'll have a look through the manual.
If that doesn't work maybe lift LDRQ0 from the superIO and attach to that?
BTW I bought a generic X99 motherboard from aliexpress, maybe it has different BIOS options
It's in the GPIO registers. You need to refer to the register 48h of the host LPC controller which sets the base address for those registers. In my case it's 500h.
(LATE EDIT: Just realized something. With GPIO registers placed in 500h this board cannot use WSS which usually resides in 530h, unless the game allows moving it to somewhere else. Don't know if it's possible to move the base address at this point. RUBY-9719VG2AR, on the other hand, places GPIO registers in 480h. Should be noted that due to the GPIO registers being in this range and accessible, some system information tools like AIDA16 would incorrectly suggest that my board has WSS installed, which is clearly not the case. I'm afraid this might end up confusing some WSS-capable games as well.)
I haven't checked all registers, only the first one (which contains the bit controlling whether LDRQ1# is GPIO23). However, in my case the corresponding bit (bit 23) is not set so LDRQ1# is indeed LDRQ1#.
I think I need to look for ways to actually probe/test the LDRQ1# signal to see if it's really working. Regardless, I'm considering taking off the heatsink (again) for an inspection when I have time...
EDIT: Don't know this part might be relevant. It was mentioned several pages ago...
myne wrote on 2023-04-26, 08:57:
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the PCH that supports two LPC bus masters, it drives 0010 for the START field for grants to Bus Master 0 (requested using LDRQ0#) and 0011 for grants to Bus Master 1 (requested using LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master.
I'm not sure if the Fintek bridge is automatically aware of which bus master it has been designated as, or something needs to be done to "tell" the bridge about it. I'm yet to find anything else related to this from the documentations...