In the mean time I had some time and decoded the DIPs for the "FIF48G PE505-16M" - inserted above. […]
Show full quote
In the mean time I had some time and decoded the DIPs for the "FIF48G PE505-16M" - inserted above.
In this pile
Bought these (retro) hardware today
I got another card.
IMG_9749r.jpg
IMG_9754r.jpg
Its totally no-name ("CE 49107"?) and has 1 bank of 4164 chips on it (=64 kb). 6 banks in total, are 3MB if filled with 256k chips.
1 DIP block with 6 switches (JP1), another one with 8 switches (JP2).
Replaced the 64k with 256k chips and...:
JP1 has no impact on XMS. (Set to 12345x)
JP2:
1234x6xx 9,5
x234x6xx 9,5
12345xxx 9,0
1234xxxx 8,5
xxx456x8 6,0
x2x4567x 4,0
x2x4x67x 3,5
x2x456xx 2,0
xxx456xx 2,0
xxx45xxx 1,0
x2x45xxx 1,0
12x45xxx 1,0
12x4x6xx 1,5
123xxxxx 512
x2x4x678 above 6mb
xx345xxx above 6mb
--> working 😎 😎 😎
____
EDIT:
SW 1,2: seem to have no impact? Set to OFF.
SW 4: set to ON ...otherwise counting at POST stops below 1024k
SW 35678: see below
Still need to figure out how to set steps at 128/256/384 kb. Should be related to SW 1,2,4,5.
0M 512K --- SW35678
1M 0K --- x5xxx verified
1M 512K --- xx6xx verified
2M 0K --- x56xx verified
2M 512K --- xxx7x
3M 0K --- x5x7x
3M 512K --- xx67x verified
4M 0K --- x567x verified
4M 512K --- xxxx8
5M 0K --- x5xx8
5M 512K --- xx6x8
6M 0K --- x56x8 verified
6M 512K --- xxx78
7M 0K --- x5x78
7M 512K --- xx678
8M 0K --- x5678
8M 512K --- 3xxxx verified
9M 0K --- 35xxx verified
9M 512K --- 3x6xx verified
10M 0K --- 356xx
10M 512K --- 3xx7x
11M 0K --- 35x7x
11M 512K --- 3x67x
12M 0K --- 3567x
12M 512K --- 3xxx8
13M 0K --- 35xx8
13M 512K --- 3x6x8
14M 0K --- 356x8
14M 512K --- 3xx78
15M 0K --- 35x78