debs3759 wrote on 2024-06-12, 15:23:

There are certainly some 90 MHz in collections, but only marked as 90 MHz, not P100 or PR100

I like to see that. The only 90's I've seen are P90+GP/80MHz.

Sphere478 wrote on 2024-06-12, 21:51:

60x1.5 90x1 45x2 […]
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60x1.5
90x1
45x2

Some cyrix chips supported 1x but Idk if that one did.

Many around that time, only had bf0 so only two multiplier options. Which was usually 1.5 and 2x. I’m basing this on other chips, I really haven’t messed with these slower cyrix chips much. So feel free to correct. But motherboatds of that time usually had only bf0

bf1 came along around 133-166 era

Bf2 intel and bf2 amd/cyrix (different pins) came along around the 233-266 era.

Technically, it is possible to have 4 settings with one register. Pull down, pull up, floating. And a forth if you tie it to a modulating signal. Some 486 chips did this for setting I think 2 or 2.5x I think it was dx4? Tying it to breq? Signal? Trying to remember. (Don’t quote)

Anyway, having only one register suggests only 2 multiplier settings. And only 2 were typical for socket 5

6x86 and 6x86L do not support half step multipliers. Only 1X, 2X, 3X and 4X. So that rules out 1.5x60=90MHz.
If only BF0 pin is present, then probably only 2X and 3X are selectable by jumper. The other settings should be accessible by running a software utility.

Seems only 2x and 3x are advertised to be supported on this IBM branded cyrix datasheet.

So 45mhz and 30 mhz fsb

https://datasheets.chipdb.org/IBM/x86/6x86/6x86_ALL.pdf

Seems 6x86L was a different core. Anyone have a datasheet for that?
https://en.m.wikipedia.org/wiki/Cyrix_6x86

I didn't get the impression that 6x86L uses a different core. It's just die-shrunk and split rail voltage.

Anonymous Coward wrote on 2024-06-13, 01:46:

I didn't get the impression that 6x86L uses a different core. It's just die-shrunk and split rail voltage.

semantics. If the core shrunk and voltage split. I consider it different. Curious if cyrix kept the same core code name though?

Edit

M1 vs M1L
https://en.m.wikipedia.org/wiki/Cyrix_6 ... el%20later.

M1
M1L (Low voltage)
M1R (3M to 5M)
MII (MMX)

The wiki lists these cores, but it’s interesting as in testing we can see performance differences between the MII offerings. Those went through a number of core shrinks and apparently also some internal reconfiguring.

Supposedly at least 3 die processes were used for the classic 6x86.

.65u --> .5u --> .44u

Anonymous Coward wrote on 2024-06-13, 03:38:

Supposedly at least 3 die processes were used for the classic 6x86.

.65u --> .5u --> .44u

And up to 11 layers