Since U43 is empty you’ll not be able to use the VLB in master and slave mode, it'll work only in slave mode. For your setup I believe that you should set both J29 and J39 to 2&3. Also set the J20 for 0 wait states.

https://theretroweb.com/motherboard/manual/32938.pdf

dominusprog wrote on 2024-05-29, 20:00:

Since U43 is empty you’ll not be able to use the VLB in master and slave mode, it'll work only in slave mode.
https://theretroweb.com/motherboard/manual/32938.pdf

Yes, but what does that mean?
Can I only install one VLB card?

ux-3 wrote on 2024-05-29, 20:16:

dominusprog wrote on 2024-05-29, 20:00:

Since U43 is empty you’ll not be able to use the VLB in master and slave mode, it'll work only in slave mode.

Yes, but what does that mean?
Can I only install one VLB card?

You can install one or two VLB cards, as long as the cards only respond to actions generated by the processor ("slave"), and do not try to access your main memory on their own ("master"). This is completely different from the terminology used by IDE: You do not need to configure your VL cards as master and slave, like you do with two hard drives.

Unless you have a VL SCSI controller like the Adaptec 2842, you will likely only have slave devices, and it will work perfectly with the "slave only" setting. If you install two cards at 40MHz or higher, you might need to fiddle around with the "compatibility jumpers" to find a configuration that works stable.

dominusprog wrote on 2024-05-29, 20:00:

For your setup I believe that you should set both J29 and J39 to 2&3.

Setting this or Mode 1 will cause read errors from CF. Only mode 0 works. (that is settled then)

mkarcher wrote on 2024-05-29, 20:25:

you will likely only have slave devices, and it will work perfectly with the "slave only" setting.

Good to know, they are slaves then.

mkarcher wrote on 2024-05-29, 20:25:

If you install two cards at 40MHz or higher, you might need to fiddle around with the "compatibility jumpers" to find a configuration that works stable.

That would be setup zero then. The others fail.

The interesting thing is: The pauses in music happens only with my VLB graphics, when the CF cards LED goes on bright (longer read). It doesn't happen, when I use my non VLB VGA card. The choice of IO (ISA or VLB makes no difference).
The VLB graphics card somehow causes these pauses even if alone on the VL bus. Changing the cards jumper for >33 MHz makes no difference.

Edit:
I also swapped the soundcard from ESS to Creative, made no difference.
It seems as if the VLB VGA card causes this. It is an S3 P86C805 chip, 1MB (Miro Crystal 8S).

Hello all, i got similar doubts here..
I have a vlb vga and IO card, can i place the vga anywhere? do she loose performance?
If i change my dx2-66 to a Dx2-80 fsb 40, will be stable with both cards? Should vga with fsb 40 be at slot 1?

Thank you

pitchshifter wrote on 2024-08-01, 14:52:

I have a vlb vga and IO card, can i place the vga anywhere? do she loose performance?
If i change my dx2-66 to a Dx2-80 fsb 40, will be stable with both cards? Should vga with fsb 40 be at slot 1?

Both your VGA and your I/O card are "slave devices" and work in any VL slot (unless you are calling and Adaptec 2842 SCSI controller "I/O card" to be humble). All three slots provide the same performance, so just looking at digital signals, there should be no difference in what card gets put where (assuming no slot has bent contacts, of course...). At 33MHz, everything will likely work fine with both cards. At FSB40, you might or might not get issues. There is no general rule of thumb on how to distribute the cards for maximum compatibility, because the optimal configuration may depend on the trace layout on the mainboard, the signal drive strength of the CPU you installed and the load characteristic and trace lengths on the cards you install. Shuffling cards around might help in borderline cases.

Your BIOS setup might have a setting called "LDEV decode" or "ELBA sampling point", which can be set to "T1/T2" or "early/late". Chosing "late" or "T2" decreases bus performance, but gives VL cards more time to claim a cycle. At 40MHz, the official recommendation is to use late decoding, whereas at 33MHz, early decoding may be used. As I understand it the "<=33 / >33MHz" jumper on many VL boards (which oftentimes just affects one of the "system type identification" pins on the VL connector) is used to inform cards on the speed required to claim the cycle. Most cards just ignore it, and claim cycles as fast as they can, which works at 40MHz most of the time even if the chipset uses "early decoding". Anyway, if you get issues at 40MHz, changing this setting to "late" (assuming you have it in your setup) might help.

IDK if it was just coincidence, or a "feature" of the mostly VIA based motherboards I had, but all my performance VLB builds back in the day, ended up with Graphics nearest the CPU and the I/O furthest away from the CPU with an empty slot in between if necessary. Anyway, that's what worked for me when doing 40Mhz plus.

I am using a 486-40, and I found no new problems at 40. If I went down to 33, no issue disappeared.

This board is only 5v, although theres variants with 3.3v. Aldo i have in the pcb the place for the voltage regulator, but i will try the dx2 80 from It´s ST that works with 5v.
I will try and inform you abou the results, it its buggy or not 😀~
This board is weird, i cant get vga from isa cards, only VLB ones.

Check you haven't got a mono/color jumper set to mono, it might force it for ISA and ignore it for VLB

Edit: I think I've seen a sneaky little cryptic CMOS setup option, maybe in advanced chipset setup on some boards that said something like "Local Bus Graphics" en/dis, which would either enable onboard, PCI, or VLB and disable ISA depending on system.

mkarcher wrote on 2024-08-01, 18:03:

pitchshifter wrote on 2024-08-01, 14:52:

I have a vlb vga and IO card, can i place the vga anywhere? do she loose performance?
If i change my dx2-66 to a Dx2-80 fsb 40, will be stable with both cards? Should vga with fsb 40 be at slot 1?

Both your VGA and your I/O card are "slave devices" and work in any VL slot (unless you are calling and Adaptec 2842 SCSI controller "I/O card" to be humble). All three slots provide the same performance, so just looking at digital signals, there should be no difference in what card gets put where (assuming no slot has bent contacts, of course...). At 33MHz, everything will likely work fine with both cards. At FSB40, you might or might not get issues. There is no general rule of thumb on how to distribute the cards for maximum compatibility, because the optimal configuration may depend on the trace layout on the mainboard, the signal drive strength of the CPU you installed and the load characteristic and trace lengths on the cards you install. Shuffling cards around might help in borderline cases.

Your BIOS setup might have a setting called "LDEV decode" or "ELBA sampling point", which can be set to "T1/T2" or "early/late". Chosing "late" or "T2" decreases bus performance, but gives VL cards more time to claim a cycle. At 40MHz, the official recommendation is to use late decoding, whereas at 33MHz, early decoding may be used. As I understand it the "<=33 / >33MHz" jumper on many VL boards (which oftentimes just affects one of the "system type identification" pins on the VL connector) is used to inform cards on the speed required to claim the cycle. Most cards just ignore it, and claim cycles as fast as they can, which works at 40MHz most of the time even if the chipset uses "early decoding". Anyway, if you get issues at 40MHz, changing this setting to "late" (assuming you have it in your setup) might help.

are you familiar with what the BIOS settings:

"VESA Master Cycle: Delay ADSJ/Non-delay ADSJ"
and
"Delay Internal ADSJ: Disabled/Enabled"

could refer to with respect to VLB? This is an ALi chipset with Phoenix BIOS

maxtherabbit wrote on 2024-08-02, 20:41:

are you familiar with what the BIOS settings: […]
Show full quote

are you familiar with what the BIOS settings:

"VESA Master Cycle: Delay ADSJ/Non-delay ADSJ"
and
"Delay Internal ADSJ: Disabled/Enabled"

could refer to with respect to VLB? This is an ALi chipset with Phoenix BIOS

I can guess what this setting means, but I don't know for sure. "ADS" is the name of the signal that is issued by the initiator (master) and tells any potential target (slave) that there is a valid cycle definition (address and cycle type) on the lines A0..A31, M/IO, D/C and R/W. ADS is usually driven by the master at the same time by the initiator as the cycle definition signals, which must be some minimum time earlier to the rising edge of the CLK signal, at which the ADS signal "is effective". Targets should look at ADS at the rising edge of the clock, and if they detect ADS at that point, they can assume that the address has been on the bus for "some time". This time is called "address setup time with respect to CLK". Usually, a master implementation does not know when the clock is going to appear, and sets up the cycle definition e.g. 10ns earlier, but instead, the cycle definition and ADS appear some time after the previous clock. Let's assume this is 15ns after the previous clock. At 33MHz bus speed, the clock period is 30ns, so 15ns after the previous clock provides 15ns setup time. At 40MHz bus speed, the clock period decreases to 25ns, so the setup time seen by the target shrinks from 15ns to 10ns, and at 50MHz FSB clock, the cycle time is just 20ns, so a signal appearing 15ns after the previous clock is only valid 5ns before the next clock, which may be too short for peripherals. Delaying ADS, so that it gets picked up one clock later (either every time, or if it is "too late" inside the current clock cycle) will ensure a longer setup time, but at the same time cost one FSB clock per cycle that is affected by "delaying ADS".

So in short: "Enable" generates a certain kind of waitstate at the start of a cycle, that can be used to make the system stable at high FSB clocks.

Thanks. Wonder what the 'J' part could be

maxtherabbit wrote on 2024-08-03, 15:50:

Thanks. Wonder what the 'J' part could be

Maybe some convention to indicate an active low signal, like "/ADS", "nADS", "ADS*" or ADS with a bar over it. ADS on the 386/486/Pentium FSB is active low. It might also be a qualifier for some internal or forwarded version of the ADS pin that is likely connected to both 486 /ADS pin and the VL /ADS pin. Most likely chipset can distinguish VL master cycles from other cycles using the state of the FSB arbitration unit, not by having different ADS pins for VL and FSB.

Hi again, i only got now the dx2 80 from It´s ST and i must say that at leat with me its bugs with the vlb controller working at 40fsb. It freezes graphs.
With a Isa controller it works fine, comparing with the intel dx2-66 speedsys gone from 24.91 to 32.21.
3dbench from 44.5 to 51.7, although Doom showed little improvment, 25.61 to 27.34.
Im happy anyways 😜