Neat !

How did you velify the 5V tolerance on the 3.3V chips ? Checking for excess current on the IO pins ?

Yes, extensively measured with a scope. Most boards anyway fail to drive proper 5V on their DRAM address lines for long.
Also cross checked to the fact that Compaq and others like Memory Masters are also using a bunch of these chips on 5V modules. https://www.ebay.com/itm/124443425899

So far I've used the A1 board with my 486 Gemlight board for almost 6 months (next week December 12).

If you want to be extra safe you can always stick to just using the 5V chips. I had considered making a level shifted buffered module, but the required shifters increase complexity and cost unreasonably.
maybe in future when I decide to make a parity module.

Ok, good ~

I have one suggestion regarding the SIPP holes, they should be moved higher up. I had them at pretty much same height on 4MB SIMMs I made and I had a report of the holes aligning with contacts of the socket on one mobo, making the sticks not work until holes were filled with solder.

I like the logo *notbiasedatall* 🤣

Ah, thanks for that suggestion. I had some concerns about the hole height as well.
Might just adjust that later when I got time.

I just found this 2 videos from some other user:
https://www.youtube.com/watch?v=oXZWF6gDNLI
https://www.youtube.com/watch?v=FNOqEWzRiBQ

He scraped some high density server EDO RAM DIMM to get cheap 3,3V chips and he 1st tried it like you without any voltage level shifter. Then he discovered that some signals are about 3,6V levels while others goes up to 5v and the chips are then running out of spec. He made 2nd revision with proper level shifters but there was some bug. He doesn't explained it much clear what was the root cause of problem. He tried some level shifters from TI with automatic bidirectional control (without dedicated direction pin) and seems that some with PP I/Os caused problems while those with OD I/Os works. He then used OD version with pull ups and successfully booted.
It seems that final PCB design is not available yet. Does someone have more precise explanation what problem he had and how fixed it?
It would be also useful for making some 64MB 72pin SIMMs that are similar rare...

RayeR wrote on 2024-10-08, 16:07:

Does someone have more precise explanation what problem he had and how fixed it?

I think the problem was "it doesnt feel right connecting directly to 5V bus", because otherwise it just works.

Why/what signal was connected to 5V bus to what IO pin of shifter? In case of constant voltage level he coul just use 3.3V output of LDO instead of 5V via shifter. I didn't find the schematic of shiftered version anywhere so I don't know. Do you have some direct contact to BuB? I see just YT channel...

I mean going to the shifter design in the first place after just the voltage reg version like in 0xCats design was Youtuber overthinking it.

As he show on YT on scope some signals reached 5V levels so using level shifter seems to me the right (safe) way. I just wonder what issue he had with shifter on his 1st design as it was not explained in deep. I cannot find direct contatct to Bub, just his YT channel...

BTW I just soldered four 4MB 30p SIMMs on PCB design by Alex G. I sacrified one 16MB EDO 60ns 70p module to get chips. I ommited the parity chip coz I cannot find any source. But it should work on some 386 and most 486 with parity checking disabled. Just tested in one 486SLC2 board with opti chipset and they works, Memtest passed... I think that 16MB would be enough for me yet... 😀

RayeR wrote on 2024-10-09, 13:20:

Do you have some direct contact to BuB? I see just YT channel...

You may find him in the forum under the nickname "BitsUndBolts". His last thread is this one.

Aha, he's also here, thanks.