Maybe there's edge cases where you've got special graphics like Tandy or PGA and you want just enough kick to make Kings Quest IV less laggy or something.

douglar wrote on 2024-12-16, 14:47:

How do these rules work?

I do not understand the question, what rules?

BitWrangler wrote on 2024-12-16, 15:00:

Maybe there's edge cases where you've got special graphics like Tandy or PGA and you want just enough kick to make Kings Quest IV less laggy or something.

In my case I really like the megapc but it is ultimately a cacheless 386sx system... even a +10% speedboost can make a nice difference - from scrolling in Monkey Island to have Turrican2 output at 20khz instead of 14~16khz... so you are always looking for ways to make it a little better but 486slc upgrade in this case is not something that will give that speed boost. It is an OEM system with integrated vga/i-o and only 1 free isa slot that you use for sound so there is no way to replace the vga or mess with BIOS settings/waitstates/clocks - even with the 486slc-aware BIOS.

keropi wrote on 2024-12-16, 15:07:

douglar wrote on 2024-12-16, 14:47:

How do these rules work?

I do not understand the question, what rules?

Back around 1990, the rule was that you wouldn't notice an upgrade unless you doubled your clock speed. If you upgraded to a computer that was only 20% faster, you were wasting your money. And the third rule I added for the vogons crowd for humor.

"Does it make sense to swap those CPUs?"

https://www.youtube.com/watch?v=yIGfu_llnXc

He goes over the which pins do the cache control and how they are mapped differently between the 486slc and the 386sx.

douglar wrote on 2024-12-20, 13:18:

"Does it make sense to swap those CPUs?"

https://www.youtube.com/watch?v=yIGfu_llnXc

He goes over the which pins do the cache control and how they are mapped differently between the 486slc and the 386sx.

The PCChips M396F ver. 2.x and 3.0 motherboards do support both the Am386SX/SXL and the Cx/TI486S(X)LC CPUs. The missing pin connections (pins 29 & 30) on these particular motherboard revisions are not mandatory for these CPU models. "Cyrix cache enabled" BIOS option provides working Cx/TI486S(X)LC CPUs L1 cache without KEN (pin 29) and FLUSH (pin 30) connections to the chipset. IIBEN (pin 29) and SMIRDY (pin 30) are needed only for the low-voltage Am386SXLV CPUs.

The other board from the video (Biostar MB-1325/1333ACA-S) is unknown to me.

Thanks for the vid, looks like my quite similar PT-319A boards are gonna do about the same thing then. I don't know if I will get both working or whether one will become a CPU donor.

This video made me investigate Cyrix support subject 😀

analog_programmer wrote on 2024-12-20, 14:02:

The PCChips M396F ver. 2.x and 3.0 motherboards do support both the Am386SX/SXL and the Cx/TI486S(X)LC CPUs.
The missing pin ... FLUSH (pin 30) connections to the chipset.

Half assed BIOS support, BARB fallback mode only leaving performance on the table Re: Register settings for various CPUs

rasz_pl wrote on 2024-12-22, 05:27:

Half assed BIOS support, BARB fallback mode only leaving performance on the table Re: Register settings for various CPUs

I don't know if FLUSH is set by BIOS option "Cyrix cache". Maybe the BIOS sets only KEN - enable cache. Or who knows. Apparently no one making YT videos with M386F mobo and the Cx486SLC bothered to read the CPU datasheets and show any adequate cache settings (using something like CX486.EXE) and tests. My M396F v.3.0 is with Am386SX so I can't test any CPU L1 cache settings.

The question was about the missing connections on pins 29 and 30. This is not fatal, since the cache control registers of 486S(X)LC processors can be set from the BIOS or by software.

Without pin 30 you are limited to fallback BARB mode. Cant enable Flush without /FLUSH pin wired.

rasz_pl wrote on 2024-12-22, 10:31:

Without pin 30 you are limited to fallback BARB mode. Cant enable Flush without /FLUSH pin wired.

In other words, if FLUSH signal is missing (pin 30 is not connected to chipset or other cache controller) there's absolutely no matter if FLUSH register bit is set to enabled or disabled and the only option for cache control is the one related to BARB register bit. Right? It seems like this is also valid for KEN (cache enable) signal. So, what is doing the "Cyrix cache enable/disable" option in the BIOS, if cache is permanently disabled by internal CPU connection and there is no KEN signal from chipset?

analog_programmer wrote on 2024-12-22, 11:15:

In other words, if FLUSH signal is missing (pin 30 is not connected to chipset or other cache controller) there's absolutely no matter if FLUSH register bit is set to enabled or disabled and the only option for cache control is the one related to BARB register bit. Right? It seems like this is also valid for KEN (cache enable) signal. So, what is doing the "Cyrix cache enable/disable" option in the BIOS, if cache is permanently disabled by internal CPU connection and there is no KEN signal from chipset?

Leaving FLUSH# pin floating and enabling the function in the control register is a bad idea. IIRC that pin has no resistor and thus can randomly read as zero, which is active signal. This will cause the CPU to flush cache and it's not a free operation. It will slow down, possibly quite a lot if the signal ends up being asserted for every instruction executed.

As for KEN, it works in the opposite way. Wih KEN disabled in control register the cache is always enabled, not disabled. So in other words everything is set to cacheable. This is exactly why the CPU has 4 (and later ones even more) special exclusion zones that can be set up to be non-cacheable. To work around lack of proper KEN from mobo side. You just set these zones statically knowing what is and isn't installed in the system.

And for the earlier questions regarding the use of SoundBlaster DMA and BARB - yes, it causes flushes and performance degradation. But it's not terrible on DLC class chips, especially if the mobo has its own cache that won't be affected. The impact on SX/SLC chip with a bare mobo would be greater but then again if you are running a game like Doom on such system it's already crawling, even 10% performance loss is not noticable either way.
The SB (or floppy) DMA is not the worst offender when it comes to BARB setting, the non-hidden memory refresh is.

Deunan wrote on 2024-12-22, 12:59:

Leaving FLUSH# pin floating and enabling the function in the control register is a bad idea. IIRC that pin has no resistor and thus can randomly read as zero, which is active signal. This will cause the CPU to flush cache and it's not a free operation. It will slow down, possibly quite a lot if the signal ends up being asserted for every instruction executed.

Nope. Unconnected FLUSH pin don't cause floating signal, it's internally connected through pull-up resistor. RTFM.

Deunan wrote on 2024-12-22, 12:59:

As for KEN, it works in the opposite way. Wih KEN disabled in control register the cache is always enabled, not disabled. So in other words everything is set to cacheable. This is exactly why the CPU has 4 (and later ones even more) special exclusion zones that can be set up to be non-cacheable. To work around lack of proper KEN from mobo side. You just set these zones statically knowing what is and isn't installed in the system.

Unconnected KEN pin also don't cause floating signal, it's internally connected through pull-up resistor. Again, RTFM.

Bonus stage - brief L1 cache logic:

P.S. Actually, why I'm bothering with how a cache of the Cx/TI486S(X)LC processor works when I don't have one, and those who do, don't even want to open the CPU's datasheet and try some combinations of settings in the M396F's BIOS and by software?

analog_programmer wrote on 2024-12-22, 14:14:

Nope. Unconnected FLUSH pin don't cause floating signal, it's internally connected through pull-up resistor. RTFM.

Indeed it is, I've must've confused it with some other input. Or perhaps with the true 486. However there is one more possible issue here, not all mobos leave the unused 386SX pins floating. Some tie them to GND (or VCC) which would be a problem.

analog_programmer wrote on 2024-12-22, 14:14:

Unconnected KEN pin also don't cause floating signal, it's internally connected through pull-up resistor. Again, RTFM.

Where did I claim KEN is floating?

analog_programmer wrote on 2024-12-22, 14:14:

Bonus stage - brief L1 cache logic:

Yeees? I'm not sure I follow...

Deunan wrote on 2024-12-22, 14:28:

However there is one more possible issue here, not all mobos leave the unused 386SX pins floating. Some tie them to GND (or VCC) which would be a problem.

Do not mess 386SX CPUs here. Intel's 386SX pins 29 and 30 are "NC" = not connected/not in use. For the Am386SX/SXL pins 29 and 30 I already wrote - they're only used in low voltage CPU version Am386SXLV. And the M396F mobo is not compatible with 3.3 V CPUs like Am386SXLV.

analog_programmer wrote on 2024-12-22, 14:43:

Do not mess 386SX CPUs here. Intel's 386SX pins 29 and 30 are "NC" = not connected/not in use.

And we all know the mobo manufacturers would never, ever, connect such pins to something - for example because it made routing power planes easier, or just because of they could. It's not like I have seen it and had to lift the pins of anything.

I have some experience with these DLC/SLC chips (I've swapped a dozen 386 CPUs, both SX and DX) and their requirements regarding L1. I've routed wires from the mobo chipset and KB controller to fix some of the issues. I've written BIOS hack for one particular mobo. It's just it has been a few years now and I don't remember all the details, and I'm not about to re-read the datasheet every time I answer these posts. I did use "IIRC" and you did your due diligence and checked. That's how it's supposed to work.

I can tell though you are unhappy with my input so I guess Merry Xmas, I'm outta here.

I was curious of "Cyrix cache enable/disable" BIOS option - what it sets in registers and how it makes L1 cache on 486S(X)LC to work in some extend (according to BuB's video), but obviously no one here knows for sure.

Ok. You've done this and that, but you don't remember exactly what and why... And I don't see any point of someone's freewriting from memory if he's too lazy to open the datasheet to recall.

Happy hanukkah and even more happy what ramadan there is in December! 😁

Deunan wrote on 2024-12-22, 12:59:

And for the earlier questions regarding the use of SoundBlaster DMA and BARB - yes, it causes flushes and performance degradation. But it's not terrible...
The SB (or floppy) DMA is not the worst offender when it comes to BARB setting, the non-hidden memory refresh is.

feipoa just tested sound without/with Barb:
>DOOM w/sound = 3689 = 20.25 fps
>DOOM w/sound = 4420 = 16.90 fps BARB

Not bad at all. Now we are only missing hidden refresh to have full picture 😀

analog_programmer wrote on 2024-12-22, 15:32:

I was curious of "Cyrix cache enable/disable" BIOS option - what it sets in registers and how it makes L1 cache on 486S(X)LC to work in some extend (according to BuB's video), but obviously no one here knows for sure.

the answer is "it depends". For example on feipoa/pshipkov Gemlight MB386-40-SYM BIOS misconfigures CPU for FLUSH mode while not wiring FLUSH pin 😀 and doesnt enable BARB mode while enabling L1 cache = wont work with floppy/bus mastering controller.

rasz_pl wrote on 2024-12-22, 16:22:

the answer is "it depends". For example on feipoa/pshipkov Gemlight MB386-40-SYM BIOS misconfigures CPU for FLUSH mode while not wiring FLUSH pin 😀 and doesnt enable BARB mode while enabling L1 cache = wont work with floppy/bus mastering controller.

This is а complete mess 🤕 Maybe there's a way to fix all of this through a software register setting. Maybe... or then again, maybe not 😁

It seems like BuB's channel owner is lucky with his partially working 486SLC L1 cache on a M396F motherboard. I've never considered an upgrade from Am386SX to a 486SLC CPU on my M369F mobo, but it wouldn't cross my mind to do such a thing in the future either, just to see what happens with the L1 cache control registers depending on the BIOS "Cyrix cache" setting.

analog_programmer wrote on 2024-12-22, 11:15:

So, what is doing the "Cyrix cache enable/disable" option in the BIOS, if cache is permanently disabled by internal CPU connection and there is no KEN signal from chipset?

I just happened to have my M396F v2.7 mobo with a factory-installed Cx486SLC-40MP close enough to my test bench to try this.

The BIOS option enables BARB, according to cyrix.exe -q output.
Enabling FLUSH and keeping BARB disabled via cyrix.exe works without issues if I have the BIOS option disabled - didn't test it with it enabled.

Shareware Doom 1.9 DEMO3 timedemo with minimal screen, low detail, sound channels to 8 with a CT2290 and mouse enabled:
FLUSH enabled - 3139 realtics - 23.794 fps
BARB enabled via BIOS - 3520 realtics - 21.219 fps

The performance difference is noticeable enough that the DMX sound library pitch fluctuation with poor performance is significantly more audibly present with BARB enabled compared to FLUSH.

DEAT wrote on 2024-12-22, 16:58:

I just happened to have my M396F v2.7 mobo with a factory-installed Cx486SLC-40MP close enough to my test bench to try this.

The BIOS option enables BARB, according to cyrix.exe -q output.

Thanks for the information. So, the BIOS "Cyrix cache enable" only sets BARB register bit to enabled.

DEAT wrote on 2024-12-22, 16:58:

Enabling FLUSH and keeping BARB disabled via cyrix.exe works without issues if I have the BIOS option disabled - didn't test it with it enabled.

Can you test if there's some difference in system speed comparing this result when FLUSH bits = set enabled and BARB bit = set disabled with three more cases:
1) FLUSH bits = set disabled, BARB bit = set disabled
2) FLUSH bits = set enabled, BARB bit = set enabled
3) FLUSH bits = set disabled, BARB bit = set enabled

I think, changing the FLUSH register setting will give no difference, but just to be sure.