myne wrote on 2025-01-01, 16:59:

Why is that not mentioned anywhere?!

It is considered standard EE knowledge taught at uni. You can find formula for calculating crosstalk in 'High Speed Digital Design: A Handbook of Black Magic' by Dr. Howard Johnson on page 190 192
Great podcast with the guy https://theamphour.com/the-amp-hour-77-winsom … eform-wizardry/

rasz_pl wrote on 2025-01-01, 22:28:

myne wrote on 2025-01-01, 16:59:

Why is that not mentioned anywhere?!

It is considered standard EE knowledge taught at uni. You can find formula for calculating crosstalk in 'High Speed Digital Design: A Handbook of Black Magic' by Dr. Howard Johnson on page 190 192
Great podcast with the guy https://theamphour.com/the-amp-hour-77-winsom … eform-wizardry/

One of the few books, I still own from my education, very, very useful

rasz_pl wrote on 2025-01-01, 22:28:

myne wrote on 2025-01-01, 16:59:

Why is that not mentioned anywhere?!

It is considered standard EE knowledge taught at uni. You can find formula for calculating crosstalk in 'High Speed Digital Design: A Handbook of Black Magic' by Dr. Howard Johnson on page 190 192
Great podcast with the guy https://theamphour.com/the-amp-hour-77-winsom … eform-wizardry/

Fair enough.
I wonder why they didn't give at least 2 examples though. eg 12mil at with x board spacing, 5mil at y.

The worst thing you can do, is give customers a choice.

myne wrote on 2025-01-01, 06:04:

Oh well, here's the progress so far.

Please do not fogret the BR1/BR3 choice jumper 😀 It is THE reason there was a need for a new adapter in the first place.

Also I say why don't we all check our PPro/P2-Overdrive CPUs to see if any of them uses VccCache? Because if not, I suggest not routing it at all.
PPro 200 MHz 256K / 512K and a P2-Overdrive I had my hands on doesn't use it. All VccCache pins are unconnected on those CPUs.
I have never tested PPro 1024K.

You're welcome to update it 😉

Many hands make light work...

While I'm taking a break with PPro project at least until Spring, I can upload scans of Mentat's Asus clone PCB, if anyone's interested.

Couldn't hurt.
I feel like I don't know enough to design one that works.
Impedence is still somewhat of a mystery to me,but apparently critical to design.

BTW what is br1/br3? Afik br1-3 are bits requests and br1 is the only bidirectional one. No?

myne wrote on 2025-01-07, 13:17:

Couldn't hurt. I feel like I don't know enough to design one that works. Impedence is still somewhat of a mystery to me,but appa […]
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Couldn't hurt.
I feel like I don't know enough to design one that works.
Impedence is still somewhat of a mystery to me,but apparently critical to design.

BTW what is br1/br3? Afik br1-3 are bits requests and br1 is the only bidirectional one. No?

BR is Bus Request. It's kind of a small pseudo-bus for arbitration between the CPUs and the chipset in multiprocessing mode. From what I've seen on a scope, there's definitely more going on than just being a bit. I.e. there's signaling there, not just steady High or Low levels.

For native PPro systems:

CPU0 | CPU1 | CPU2 | CPU3 | Chipset
BR0 -- BR1 -- BR2 -- BR3 -- BR
BR1 ---BR2--BR3---BR0 -- n/c
BR2---BR3--BR0---BR1 -- n/c
BR3---BR0--BR1---BR2 -- n/c

For 440LX (PPro orP2) and 440BX (P2 only):

CPU0 | CPU1 | Chipset
BR0 -- BR1 -- BR
BR1 ---BR0 -- n/c

For 440BX PPro only:

CPU0 | CPU1 | Chipset
BR0 -- BR3 -- BR
BR3 ---BR0 -- n/c

The problem with Slot systems is that the slot themselves carry only BR0 and BR1 contacts, as BR2 and BR3 (and the whole quad CPU system) was deprecated by this point.
So the signals needed for quad CPU system are not included neither on mobos, nor on the CPUs. Early chipsets work fine by only using BR0 + BR1 combo on PPro CPUs. 440BX doesn't. Apparently, VIA also works just fine with BR0 + BR1.

First time I started 2x PPro on 440BX, I actually manually interconnected all four BR contacts in a rotary fashion, like it would be on a native PPro board. And it suddenly worked.
The fact that it works wired as BR0 to BR3 and BR3 to BR0 is just luck. It makes possible for things to work without extra wires between the CPUs/adapters.

Oh by the way, the unused/unconnected BR# pins on the CPU still MUST be terminated with resistors. Proving there's more going on there than simply being an ID of some kind.

Sorry. Typo. Bit was meant to be bus.

Here's why your trick worked:
http://stffrdhrn.github.io/content/2019/Intel_PentiumPro.pdf
Pg 102.

Frankly, I would have expected the socket to be wired in that way, so your trick shouldn't be needed.

It just works. 2x2.5@250 2xPPro SY048/512k with #BR1->#BR3 mod , suggested by Artyom. It was great contribution of him to this thread of the ultimate PPro building . The next step is a Quad PPro / Slot 2 / serverworks systems ))

arti9m wrote on 2025-01-05, 16:02:

While I'm taking a break with PPro project at least until Spring, I can upload scans of Mentat's Asus clone PCB, if anyone's interested.

By doing this you are accepting the fact that you are messed up with your own design due to your incompetence. Just do better and upload what you want as much as you want. If you want your own clone of Asus C-P6S1 buy one and make a clone. I did not allow you to share copies and/or scans of my design. But, I’m considering to upload my design to pcbway or similar manufacturer where anyone could buy slotket pre-assembled.

Nice, I would be happy just with existing PCB without SMP support as I don't have any dual slot 1 MB... Just a curiosity, I already have Slot 8 MB and no performance advantage of PPro over PII/III in slot 1 MB but just like to see how far I can push my PPro 200/256k CPU.

Mentat-vvo wrote on 2025-01-09, 00:23:

The next step is a Quad PPro / Slot 2 / serverworks systems ))

I volunteer as a a test subject.

https://imgur.com/gallery/1uNSOIL

^.^

I just need a proper chassis for that beast and I'll be ready for a build.

RayeR wrote on 2025-01-09, 01:11:

Nice, I would be happy just with existing PCB without SMP support as I don't have any dual slot 1 MB... Just a curiosity, I already have Slot 8 MB and no performance advantage of PPro over PII/III in slot 1 MB but just like to see how far I can push my PPro 200/256k CPU.

Asus C-P6S1 and it’s clone IS SMP-capable , but not in iBX-based mobos. The best CPU to overclock is 180 MHz PPro as far as I know. And B21 trick IS working in VIA systems to set up 100 MHz FSB including SMP setup.

RayeR wrote on 2025-01-09, 01:11:

But just like to see how far I can push my PPro 200/256k CPU.

Then you should go with Mentat's design as mine will be the limiting factor, not your CPU.
I'm still sending you a copy of mine tho =)

Mentat-vvo wrote on 2025-01-09, 00:38:

By doing this you are accepting the fact that you are messed up with your own design due to your incompetence.

Badly written project assembly instructions, mismatched socket footprint, lack of thermal barriers on internal layers, that Vcache to Vcc short... Don't you talk to me about incompetence 😁
The mistake I made was at least extremely difficult to avoid so I'm owning that one. Especially considering my design actually worked on the 1st try and it was the first time ever I ordered a PCB from a factory.
The reason I'm taking a break is because I have other projects that I'd like to finish. I'm already way overbudget (time-wise) with this PPro adapter.

I regret not consulting with people in this thread. Tho in my defense I don't think many would be wanting to dig into it unless I actually had a finished product on hand.

Mentat-vvo wrote on 2025-01-09, 00:38:

I did not allow you to share copies and/or scans of my design.

I'm not asking you for a permission to upload a photo of a PCB I own. It is my full right to do anything I want with it, including clean-room reverse-engineering.
I bet you also wouldn't allow sharing modified BIOS copies you actually sell. Thankfully, those are not needed anymore.

2x112 are ok. Did test as 2.5x103 are also ok.
My dear colleague Artyom,
I don’t know who is writing bioses for you, for community, actually), but he was definitely inspired by a copy of my manually-patched bios. I must disappoint you: his automatically-patched Asus P2B-D BIOS does not work. It does not detect 2 CPUs and locks up while detects pnp devices. Anyway, your achievement in the fixing the #BR issue in dual BX is accepted. Many thanks for that. As for other - you must grow up over yourself , young man, and delete all that shit above.

Mentat-vvo wrote on 2025-01-09, 05:27:

but was definitely inspired by a copy of my manually-patched bios.

Definitely not. Mainly these were used (at least by me): https://oezmen.eu/bios/ <- Actually I recommend these for everyone even if you don't have a PPro slocket. But P2B-D one doesn't work. Working P2B-D BIOS was initially obtained from max1024, which is different from yours judging by your photos. Also note that for proper Dual CPU validation you should boot an MPS or ACPI-capable multicore OS. Linux would work.

Actually, Linux works just fine with Pentium Pro and Pentium 2 at the same time, and detects them both properly. You won't even need a BR3 fix for that as long as you put P2 in the intermedieate slot. Windows NT based systems will BSOD with "Unsupported configuration" message.
WARNING: Asus P2B-D(S) has a design flaw: voltage ID pins are shorted/shared between two slots! You will have to use P2 Klamath at ~3.3V and tape out VID pins on it.

Mentat-vvo wrote on 2025-01-09, 05:27:

As for other - you must grow up over yourself , young man, and delete all that shit above.

No.

Mentat-vvo wrote on 2025-01-09, 05:27:

I must disappoint you: his automatically-patched Asus P2B-D BIOS does not work. It does not detect 2 CPUs and locks up while detects pnp devices.

Sorry, missed that initially. You're wrong here again, I already booted both max1024 BIOS 6 months ago on video and another patched version by @kmeaw after that live onstream.
Booted, installed win2000 with MPS kernel and actually showed utilization of both CPUs.

But most importantly, if it doesn't detect 2 CPUs for you, it means your CPUs are also not synced properly (just like with my adapters) and they will NOT work in a multiprocessor OS. Possibly due to FSB being too high.