With a direct-mapped cache, each RAM memory location can only be stored in one location in cache.
For a 256K cache, you would mask off the bottom 18 bits, and that would give the address in cache.
For a 512K cache, it would be the bottom 19 bits.

The tag gives the upper part of the memory address bits so you can tell whether it is a hit or not.
If the tag is 10 bits, that means a 256K cache would handle 2^28 = 256 MB RAM, and 512K would be 512 MB.

In contrast, on a 486 board the tag is only 8 bits, so that is why it's 64 MB and 128 MB.
In both cases, the cacheable ranges are cut in half if one tag bit is robbed to keep track of the dirty/clean state of that cache line (for write-back support).

I ddidn't check the Aladdin IV datasheet, but your claim is in the banner specs of the Aladdin V datasheet. It says

Aladdin V datasheet wrote:

• Cacheable memory up to 128MB with 8-bit Tag SRAM when using 512KB L2 cache, 256MB when using 256KB L2 cache.
• Cacheable memory up to 512MB with 10-bit Tag SRAM when using 512KB L2 cache, 1GB when using 256KB L2 cache.

As jakethompson1 calculated, these numbers don't seem to make sense. Please look at pages 77 and following pages for the actual cache specification. The matter gets slightly complicated because some, but not all, revisions have a working integrated tag RAM of 16K x 10, but it seems these specifications are generally written for configurations that don't use the integrated address tag RAM. Furthermore, the chipset also has (in all revisions) an integrated 8K x 4 (also usable as 16K x 2 or 32K x 1) RAM primarily to store "valid" and "dirty" information. With 512KB cache, there are 16K cache lines of 32 bytes each, so the dirty/valid (they call it "MESI") RAM is fully occupied by for this purpose. On the other hand, at just 256KB cache, you only have 8K cache lines, so there are four integrated bits per tag line, which obviously can (or were supposed to be able to) be reconfigured as extra address lines. Note that in the datasheet revision I linked, on page 77 the configurations with 256KB cache have a shaded background which seem to indicate a "change markup", so earlier revisions had different content in those table cells. It looks like that data sheet incompletely removed the operation mode of repurposing MESI bits to address bits, so some traces are still left in, like the bigger cacheable area that include two internal address bits in addition to the 8 or 10 external address bits.

EDIT: To add support to my theory, please also have a look at the cache setup table with external tag on page 121. This is essentially a copy of the table at page 77 with added columns indicating the chipset register configuration needed to activate this configuration. That table confirms the use of the MESI RAM as 2 extra address bits for 256K cache size. It seems the editing job to remove this mode has been done quite sloppy.