I thought that AMD can't implement those pins even if they wanted as a result of their settlement with Intel?
The in circuit emulation was encumbered?

I don't know. I didn't emulate the circuit. What circuit?

Also, I'm not familiar with the lawsuit details. I just see these 4 pins on, both, Cyrix and AMD's 5x86 datasheets.

I believe those are the "set of four pins that are sampled at every clock boundary" described here: https://www.rcollins.org/ddj/Sep97/Sep97.html

I don't think anything but a special debugging motherboard would ever make use of those.

Today, we would run under an emulator to debug firmware at that level.

These 4 test pins belong to the JTAG Boundary Scan serial test interface.

https://en.m.wikipedia.org/wiki/Boundary_scan

I believe they are not used during normal operation, and can safely be left unconnected.

Jan

Chkcpu wrote on 2025-03-29, 09:33:

These 4 test pins belong to the JTAG Boundary Scan serial test interface.

I believe they are not used during normal operation, and can safely be left unconnected.

TCK may benefit from being pulled down with a resistor to avoid clocking random requests into JTAG interface - the noise from neighboring pins may couple into it.
CPU may have internal pulldowns (i've no idea really), but if you don't know for sure then it's better be explicitly pulled.

jakethompson1 wrote on 2025-03-29, 02:33:

I thought that AMD can't implement those pins even if they wanted as a result of their settlement with Intel?

I don't suppose Intel is able to prohibit AMD or Cyrix to implement an on-chip debugger with a JTAG-compliant interface. AFAIK (but I'm only partly into that story) the lawsuit just prohibited AMD from copying Intel's debugging interface AMD chips. It's well known that there was a cross-licensing agreement that allowed AMD to produce e.g. copies of Intel's 80386 processors, wihch was required for military and space qualification (having a 2nd source was the requirement). Whether that license also covered the 486 processor was the key point of the lawsuit, and from how the 486DX4 / 5x86 story went on, we notice that AMD obviously had to remove stuff related to on-chip debugging/emulation as a result, resulting in the "N" series of chips (like the 80486DX4-NV8T). As I understood recently reading processor blogs, the System Management Mode (SMM, first seen on the 386SL) for power management is mostly a slightly re-dressed in-circuit emulation (ICE) debugger execution mode (which Intel introduced with the 286 or even earlier), so this meant the N-series AMD processors also lost SMM. AMD then implemented their own implementation of a system management mode, which was not just a copy of Intel's SMM/ICE implementation, resulting in the "S" series (eg.g the 80486DX4-SV8B).

I don't see why copyright law (which likely was the key point in the SMM/ICE stuff) can be used to prevent AMD from implementing their own JTAG debugging interface, although patent law might yield some restrictions on debugging/emulation techniques offered on the JTAG interface. If I remember correctly, the JTAG interface was not bonded on a lot of Intel processors. For the classic 80486DX processors (before SMM), I vaguely remember reading in an Intel data book that only the 50 MHz model (the most expensive, top-of-the-line model) included the JTAG interface.

feipoa wrote on 2025-03-29, 01:56:

One other issue was that CLKMUL isn't wired, but I don't mind jumpering just one pin.

On some CPUs R17 is not connected, or connected to B13 instead. Such as AMD DX2 & DX4 (non WB) CPUs.

On other CPUs R17 is CLKMUL, and B13 is WB/WT select... AM5x86, Cyrix 586, Intel DX4, AMD DX2 & DX4 (WB).

From here: https://www.pchardwarelinks.com/486pin2.htm

That's an excellent all-in-one PGA168 comparison of pin assignments for various CPUs. I will be sure to look through it in detail before I alter this QFP208-PGA168 interposer. So far, my observations are as follows:

PGA R17 (CLKMUL) -----> QFP 96 (N/C)
QFP 11 (CLKMUL) -----> No trace
PGA B13 (WB/WT') -----> QFP 58 (SRESET)
QFP 64 (WB/WT') -----> PGA A13 (N/C)
PGA S4 (VOLDET) -----> QFP 60 (Vcc)
PGA A3, A14, B16, B14 (TCK, TDI, TDO, TMS) -----> No trace

Looks like I'll also need to reroute WB/WT'. Thanks for bringing this up. This is the interposer in question:

Are you aware of the great 486 pinout comparison table at http://ps-2.kev009.com/eprmhtml/eprmx/h12203.htm ? This page is very useful for all the variant specific signals, but do not trust the address pin numbering! IIRC A16 and A13 are swapped on the socket diagram. I lost too much time myself into hunting down the wrong way trusting this site (instead of the Intel PDF datasheet or an Intel dead tree data book, which I both would have had at hand, too) not understanding why the address bits behaved in an unexpected way.

PGA B13 to QFP SRESET looks like the adapter in its current state is intended to have the classic Cyrix 486 pinout on the PGA side.

Thanks for the caution.

Yes, looks like Cx486DX standard pinout.

I cross referenced name differences between Am5x86 and Cx486DX and think I've finished my analysis. I think adapting this adaptor for Am5x86 may be a bit involved.

Parenthesis () indicate the Am5x86 naming convention. PGA and QFP grid references are concerning the copper adaptor shown above.

PGA R17 (CLKMUL) -----> QFP 96 (N/C)
QFP 11 (CLKMUL) -----> No trace
PGA B13 (WB/WT') -----> QFP 58 (SRESET)
QFP 64 (WB/WT') -----> PGA A13 (N/C)
PGA S4 (VOLDET) -----> QFP 60 (Vcc)
PGA A3, A14, B16, B14 (TCK, TDI, TDO, TMS) -----> No trace
PGA A12 (HITM#) -----> QFP 65 (SMI#)
QFP 63 (HITM#) -----> PGA C12 (SMIACT#)
PGA B10 (SMI#) -----> No trace
QFP 59 (SMIACT#) -----> PGA C10 (SRESET)
QFP 58 (SRESET) -----> PGA B13 (WB/WT#)
PGA B12 (CACHE#) -----> No trace
QFP 70 (CACHE#) -----> PGA C13 (N/C)

Retro-fitting this QFP208-to-PGA168 adaptor would require:

Cut R17 trace and bodge wire R17 to QFP 11
Cut B13 & A13 traces. Bodge B13 to QFP 64 and bodge PGA C10 to QFP 58.
Cut S4 trace and bodge C10 to GND
Cut A12, C12, C10, and B13 traces. Bodge wire A12 to QFP 63, C12 to QFP 59, B10 to QFP 65, C10 to QFP 58.
Cut C13 trace and bodge wire B12 to QFP 70.

That's 9 trace cuts and 9 bodge wires. And I am assuming that the remainder of the adaptor is wired per Cx486DX. I'm not sure if this is worth the effort.

feipoa wrote on 2025-03-31, 08:29:

And I am assuming that the remainder of the adaptor is wired per Cx486DX. I'm not sure if this is worth the effort.

As the adapter originally contained a Cx486DX, it is very likely to be wired per Cx486DX, so I would be surprised if that assumption doesn't hold. You can likely skimp on the effort of modifying the adapter if you put extra effort in jumpering your target mainbaord (assuming you only want to use the Am5x86 in one specific board): You might keep the Cx486 pinout, and then jumper the mainboard to some wild AMD/Cyrix hybrid (put the jumpers for signal routing in the "Cyrix" position, put the jumpers for chipset strapping (or "trapping" as some Taiwanese vendor calls it) into the AMD/Intel &EW position). This probably only needs a minimum amount of bodges on the adapter.

The adaptor originally had a Cyrix 486DX2V (low voltage), which according to the table in the above linked URL, should have required less bodges. While the interposer looks like it was intended for Cyrix 486DX/DX2 5V, maybe it was hoped to also work with the low voltage variant and someone soldered a CPU on.

The goal is to keep the CPU+interposer floating, rather than fixing the motherboard.

I will probably do the 9 bodges at some point, although the amount of work required was not anticipated.

mkarcher wrote on 2025-03-29, 15:35:

jakethompson1 wrote on 2025-03-29, 02:33:

I thought that AMD can't implement those pins even if they wanted as a result of their settlement with Intel?

I don't suppose Intel is able to prohibit AMD or Cyrix to implement an on-chip debugger with a JTAG-compliant interface. AFAIK (but I'm only partly into that story) the lawsuit just prohibited AMD from copying Intel's debugging interface AMD chips. It's well known that there was a cross-licensing agreement that allowed AMD to produce e.g. copies of Intel's 80386 processors, wihch was required for military and space qualification (having a 2nd source was the requirement). Whether that license also covered the 486 processor was the key point of the lawsuit, and from how the 486DX4 / 5x86 story went on, we notice that AMD obviously had to remove stuff related to on-chip debugging/emulation as a result, resulting in the "N" series of chips (like the 80486DX4-NV8T). As I understood recently reading processor blogs, the System Management Mode (SMM, first seen on the 386SL) for power management is mostly a slightly re-dressed in-circuit emulation (ICE) debugger execution mode (which Intel introduced with the 286 or even earlier), so this meant the N-series AMD processors also lost SMM. AMD then implemented their own implementation of a system management mode, which was not just a copy of Intel's SMM/ICE implementation, resulting in the "S" series (eg.g the 80486DX4-SV8B).

I don't see why copyright law (which likely was the key point in the SMM/ICE stuff) can be used to prevent AMD from implementing their own JTAG debugging interface, although patent law might yield some restrictions on debugging/emulation techniques offered on the JTAG interface. If I remember correctly, the JTAG interface was not bonded on a lot of Intel processors. For the classic 80486DX processors (before SMM), I vaguely remember reading in an Intel data book that only the 50 MHz model (the most expensive, top-of-the-line model) included the JTAG interface.

Ah. That no desktop PC implementation could depend on those pins was just my greatly oversimplified/uninformed view.
Speaking of "S" 486 class CPUs, I guess you notice that sometimes people speak of their "Pentium-S". Do you think this is just because of Award BIOS of that era tacking on -S to any CPU that supported SL, or was there something more official to it?

feipoa wrote on 2025-03-31, 08:29:

Thanks for the caution. […]
Show full quote

Thanks for the caution.

Yes, looks like Cx486DX standard pinout.

I cross referenced name differences between Am5x86 and Cx486DX and think I've finished my analysis. I think adapting this adaptor for Am5x86 may be a bit involved.

Parenthesis () indicate the Am5x86 naming convention. PGA and QFP grid references are concerning the copper adaptor shown above.

PGA R17 (CLKMUL) -----> QFP 96 (N/C)
QFP 11 (CLKMUL) -----> No trace
PGA B13 (WB/WT') -----> QFP 58 (SRESET)
QFP 64 (WB/WT') -----> PGA A13 (N/C)
PGA S4 (VOLDET) -----> QFP 60 (Vcc)
PGA A3, A14, B16, B14 (TCK, TDI, TDO, TMS) -----> No trace
PGA A12 (HITM#) -----> QFP 65 (SMI#)
QFP 63 (HITM#) -----> PGA C12 (SMIACT#)
PGA B10 (SMI#) -----> No trace
QFP 59 (SMIACT#) -----> PGA C10 (SRESET)
QFP 58 (SRESET) -----> PGA B13 (WB/WT#)
PGA B12 (CACHE#) -----> No trace
QFP 70 (CACHE#) -----> PGA C13 (N/C)

Retro-fitting this QFP208-to-PGA168 adaptor would require:

Cut R17 trace and bodge wire R17 to QFP 11
Cut B13 & A13 traces. Bodge B13 to QFP 64 and bodge PGA C10 to QFP 58.
Cut S4 trace and bodge C10 to GND
Cut A12, C12, C10, and B13 traces. Bodge wire A12 to QFP 63, C12 to QFP 59, B10 to QFP 65, C10 to QFP 58.
Cut C13 trace and bodge wire B12 to QFP 70.

That's 9 trace cuts and 9 bodge wires. And I am assuming that the remainder of the adaptor is wired per Cx486DX. I'm not sure if this is worth the effort.

Look's like you are vested in this 😀

I'm surprised you are wanting to use it with an AMD seeing I see those on an interposer quite often, unless of course the price was right.

My first thought was that you had this ready for one of the 120mhz cyrix QFPs that have been on ebay for a while now....which leads me to the question- is the cyrix and amd 5x86 qfp pinout the same/ could one use the same interposer without changes??

I have a few bare interposers which are wired for Cx5x86 and Am5x86 already. I found the copper coloured interposer before I found the bare 5x86 interposers. Since the Cyrix 486DX2V80 on the copper interposer wasn't working, I thought I could re-purpose the interposer as there's no other use for it.

The issue I have with my existing Evergreen Am5x86 upgrade interposers is that they contain a weak VRM, usually with an 800 mA limit. Usually the VRM's on motherboards are ~2 A. As I am trying to push the QFP Am5x86 to 200 MHz, I'd rather use the motherboard's VRM and not alter an Evergreen upgrade board. I've found that the Am5x86 QFP's from 2001-2003 tend to overclock the best and they are cheap on eBay.

For the most part, Am5x86 and Cx5x86 targeted interposers can work with both CPUs, except that the WB/WT' pin may not be wired on Cx5x86 specific interposers. Also, the VOLDET pin may not be wired. Not having the VOLDET pin wired to GND is usually OK, unless you have a motherboard which insists on checking VOLDET and doesn't have a documented override option for the voltage. In which case, the motherboard will set 5 V to the Am5x86. Just GND VOLDET in that case.

jakethompson1 wrote on 2025-03-31, 22:53:

Speaking of "S" 486 class CPUs, I guess you notice that sometimes people speak of their "Pentium-S". Do you think this is just because of Award BIOS of that era tacking on -S to any CPU that supported SL, or was there something more official to it?

I never read "Pentium-S" in any official document, so I very much suppose it's just that Award artifact, as you said.

jakethompson1 wrote on 2025-03-31, 22:53:

mkarcher wrote on 2025-03-29, 15:35:

jakethompson1 wrote on 2025-03-29, 02:33:

I thought that AMD can't implement those pins even if they wanted as a result of their settlement with Intel?

I don't suppose Intel is able to prohibit AMD or Cyrix to implement an on-chip debugger with a JTAG-compliant interface. AFAIK (but I'm only partly into that story) the lawsuit just prohibited AMD from copying Intel's debugging interface AMD chips. It's well known that there was a cross-licensing agreement that allowed AMD to produce e.g. copies of Intel's 80386 processors, wihch was required for military and space qualification (having a 2nd source was the requirement). Whether that license also covered the 486 processor was the key point of the lawsuit, and from how the 486DX4 / 5x86 story went on, we notice that AMD obviously had to remove stuff related to on-chip debugging/emulation as a result, resulting in the "N" series of chips (like the 80486DX4-NV8T). As I understood recently reading processor blogs, the System Management Mode (SMM, first seen on the 386SL) for power management is mostly a slightly re-dressed in-circuit emulation (ICE) debugger execution mode (which Intel introduced with the 286 or even earlier), so this meant the N-series AMD processors also lost SMM. AMD then implemented their own implementation of a system management mode, which was not just a copy of Intel's SMM/ICE implementation, resulting in the "S" series (eg.g the 80486DX4-SV8B).

I don't see why copyright law (which likely was the key point in the SMM/ICE stuff) can be used to prevent AMD from implementing their own JTAG debugging interface, although patent law might yield some restrictions on debugging/emulation techniques offered on the JTAG interface. If I remember correctly, the JTAG interface was not bonded on a lot of Intel processors. For the classic 80486DX processors (before SMM), I vaguely remember reading in an Intel data book that only the 50 MHz model (the most expensive, top-of-the-line model) included the JTAG interface.

Ah. That no desktop PC implementation could depend on those pins was just my greatly oversimplified/uninformed view.
Speaking of "S" 486 class CPUs, I guess you notice that sometimes people speak of their "Pentium-S". Do you think this is just because of Award BIOS of that era tacking on -S to any CPU that supported SL, or was there something more official to it?

Pentium-S doesn't have anything to do with any 486 nomenclature. Afaik the "S" is just used to denote that it is a vanilla Pentium (non-MMX). A bios supporting both may display "Pentium-S" and "Pentium MMX" accordingly depending on the cpu installed. I assume a bios predating MMX would just display "Intel Pentium", as there was only one Pentium at that time with no need to differentiate it from any other model.