VOGONS


Reply 20 of 29, by jakethompson1

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Those SRAMs on eBay have defective ones mixed in. So a tester is almost mandatory.

Aster tag RAM has a different pinout. Did you have to change a jumper when switching away from it?

Reply 21 of 29, by clb

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It seemed like the RAM testers are all quite expensive, so I just bit the bullet and bought a set of 512KB cache RAM from eBay, from this seller: https://www.ebay.de/itm/335247348747 (much cheaper to just try that, even though of course it can be hit or miss)

The chips arrived today, put them in, and yay, it all works.

SpeedSys before (256 KB of L2 cache):

The attachment cache_before.png is no longer available

and after (512KB of L2 cache):

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this was with system RAM expanded from my original 16MB to 32MB (2x 16 MB sticks, i.e. added a new 16 MB stick):

The attachment IMG_6232.jpg is no longer available

I think I'll skip the attempt to try to go up to 64MB (at least for now).

Yay, happy.

Reply 22 of 29, by clb

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jakethompson1 wrote on 2025-01-11, 05:34:

Aster tag RAM has a different pinout. Did you have to change a jumper when switching away from it?

Oh yeah, I had to add an extra jumper. That is visible in the above photo as the white jumper in top left.

Reply 23 of 29, by clb

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Compared Dosbench Doom timedemo:
- Before (256KB L2 cache): 26.68 fps
- After (512KB L2 cache): 27.87 fps (+ 4.46% faster)

BIOS settings were at defaults:

The attachment bios_settings.png is no longer available

Reply 24 of 29, by Disruptor

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BIOS settings are very conservative.
What Cyrix do you have? DX2-80, DX4-100?

Reply 25 of 29, by clb

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It is a 80 MHz one.

The attachment Screenshot 2025-01-29 23-53-23.png is no longer available

(Oddly I could swear when my mom bought the PC for me in 1996 when I was a kid, that the PC would have been sold as a 66MHz one.. but it does have 80MHz markings and runs at that speed)

It would be interesting to poke with the different memory timing settings at some point.

Reply 26 of 29, by Disruptor

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Ok, then it would probably not work when you set your L2 cache timings to tightest 2-1-1-1 with just a single bank.
You can play with memory timings.
You probably can overclock PCI to 1:1 / 40 MHz. Be aware that the 1:2/3 option may generate an unsymmetric clock signal, if available.
Use the DOSBENCH suite (Quake, Doom) for first tests.
Be aware that written data to hard disk may be corrupted, so please do not use SMARTDRV when testing. Install test applications with conservative timings.

Reply 27 of 29, by rmay635703

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Disruptor wrote on 2025-01-30, 13:07:

Ok, then it would probably not work when you set your L2 cache timings to tightest 2-1-1-1 with just a single bank.

Something I’ve never understood is why 486 cache timings were so mediocre with respect to the available cache speeds In the era.

As an example, timing is speed it’s well understood that 20ns IS 50mhz just as 10ns is 100mhz cycle speed.

Although some 486s had 20 or 25ns cache, I had others with 15ns or even 12ns on a lowly 33mhz FSB.

Why cant I set cache to ZERO wait states at 33mhz with 15ns cache? The boards I’ve seen never have that as an option.

Reply 28 of 29, by myne

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Good, fast, cheap

Pick 2

I built:
Convert old ASUS ASC boardviews to KICAD PCB!
Re: A comprehensive guide to install and play MechWarrior 2 on new versions on Windows.
Dos+Windows 3.11+tcp+vbe_svga auto-install iso template
Script to backup Win9x\ME drivers from a working install
Re: The thing no one asked for: KICAD 440bx reference schematic

Reply 29 of 29, by jakethompson1

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rmay635703 wrote on 2025-04-04, 02:34:

Why cant I set cache to ZERO wait states at 33mhz with 15ns cache? The boards I’ve seen never have that as an option.

I think it is a matter of the terminology being mixed up.

2-1-1-1 is the fastest a 486 CPU can possibly burst read from memory, so when you set "cache wait states" in the BIOS, that is as fast as you can go, which is 25 ns (at 40 MHz) between the last 3 reads, and whatever delays in addition to the SRAM reacting to the new address also have to come out of that.

In contrast, when the BIOS lets you set "DRAM wait states" and sometimes "cache write wait states", they mean an additional wait state relative to some minimum number of wait states imposed by the chipset. e.g. "0 WS" for DRAM might really mean 3 cycles. SiS seems like they tried to avoid that confusion by calling it Slowest/Slower/Faster/Fastest instead of 0/1/2/3. This datasheet talks about it on page 11. https://theretroweb.com/chip/documentation/si … 72975850640.pdf

As you suggest, so long as you are double banked (eight chips) and willing to live with 3 cycles for a cache write (aka "1 cache write wait state"), the table on page 10 suggests that you can achieve 2-1-1-1 reads with 20 ns cache at 40 MHz, 25 ns cache at 33 MHz, and 40 ns cache at 25 MHz. In contrast in a single bank (four chip) configuration, you're stuck in 2-2-2-2 at 40MHz at best, and 3-2-2-2 at 50 MHz.