I’ve cleaned the board thoroughly and done a detailed inspection under a microscope but haven’t found any damage.

What could be causing the first ram slot not to work?

Could it be related to the floppy port that is not working either?

Is there such a thing as an SDRAM slot tester that I could insert into the faulty slot to try to determine which contacts have an issue?

With such a diagnostic, I could follow the traces to see if I can find components that are faulty.

The memory slot that has an issue is the one closest to the north bridge.
It’s possible that there is a broken solder joint under the bridge, in which case I will not be able to fix it but it would be helpful to narrow down the fault rather than making such assumptions.

I have measured each and every pin of the faulty memory slot to ground and the readings are the same as the other slots.

Why would this one slot cause the system to beep repeatedly and not POST, while the other two slots work just fine?

The only other slightly unusual thing is a whistle or whine from the coil behind the CPU slot, nearest to the AGP port.

I would really like to fix this board. Please help!

This motherboard was the one I had in the early 2000s with a 700MHz Pentium III, still have it, but avoid using for a build.

SDRAM slots are basically wired in parallel, except for some control signals like /WE, /CSx, /CAS, CKx (clock) etc. Compare the data (64) and address (14) bus pins of the first slot with the pins of the other slots, they should all be wired in parallel, if everything is fine here, then the problem is somewhere in the control or clock signals. I recommend checking pins from the top of the slots, not the bottom, this way you'll be sure that there are no cracked/dry solder joints.

SDRAM pinout site, the 72 ECC column should match the SDRAM slot pinout of this motherboard.

SSTV2 wrote on 2025-04-24, 03:16:

This motherboard was the one I had in the early 2000s with a 700MHz Pentium III, still have it, but avoid using for a build.

SDRAM slots are basically wired in parallel, except for some control signals like /WE, /CSx, /CAS, CKx (clock) etc. Compare the data (64) and address (14) bus pins of the first slot with the pins of the other slots, they should all be wired in parallel, if everything is fine here, then the problem is somewhere in the control or clock signals. I recommend checking pins from the top of the slots, not the bottom, this way you'll be sure that there are no cracked/dry solder joints.

SDRAM pinout site, the 72 ECC column should match the SDRAM slot pinout of this motherboard.

Thanks for the info and the link.

Since the slots are wired in parallel, would it be a fair assumption that the connections are good under the north bridge because the other two slots are working?

With the board not powered, I did measure the contacts of the slots from the top the other day and compared the results to the other slots. The readings were the same but I’ll do it again.

Which components on this board would be part of the control and clock signals? I’d like to check the components to see if I can find anything strange.

I’m waiting on an oscilloscope that I ordered. Hopefully it will help.

Out of interest, why do you avoid using the board in a build? It seems like a nice board. Did you have some issues with it?

byte_76 wrote on 2025-04-24, 05:49:

Since the slots are wired in parallel, would it be a fair assumption that the connections are good under the north bridge because the other two slots are working?

With the board not powered, I did measure the contacts of the slots from the top the other day and compared the results to the other slots. The readings were the same but I’ll do it again.

Yes, at least all solder joints for the slots 2 and 3 are all connected, so are the data/address buses and all the essential control signals related to them.

If slot 1 produced absolutely identical readings, compared to the other slots with the relation to ground, then cracked solder joints/vias are unlikely.

These old BGA chipsets rarely develop cracked solder joins on their own, usually it's the external forces that cause them, eg. warping of the board. Looking at the datasheet (pg. 12-17), you can notice that the majority of the DRAM bus connections are located at the opposite corner from the key pin, I'd investigate that quadrant more thoroughly. You can try pushing that corner down while simultaneously resetting the system.

byte_76 wrote on 2025-04-24, 05:49:

Which components on this board would be part of the control and clock signals? I’d like to check the components to see if I can find anything strange.

Control signals come from the northbridge, while clock is derived from the clock generator IC "ICS9148-58", there are 4 clock signals coming from it per slot - SDRAM[0:11].

byte_76 wrote on 2025-04-24, 05:49:

Out of interest, why do you avoid using the board in a build? It seems like a nice board. Did you have some issues with it?

It definitely is a nice board in terms of quality, layout and especially its clock generator's wide range clock output settings, but it uses a VIA "Apollo Pro" chipset which doesn't deliver a good perfomance compared to the 440LX/BX chipsets from intel, the memory performance is worse and AGP implementation is bad. True AGP cards (the ones that support AGP features) like TNTs Geforce or Radeon lineup will have all sorts of problems with these early slot1 VIA chipsets and their AGP GART drivers + performance will be degraded. I remember that my 700MHz pentium III OC'ed to 864MHz performed more or less like a 450MHz PII that my friend had at the time in D3D/OGL games, we both had GF4 video cards, except he had a 440BX based MB.

You can find many benchmark comparisons on the net between these VIA chipsets and intel 440 ones, I did one not too long ago, if you are interested I might unearth and post it here.

Okay so testing each pin of the memory slots from the top gives me near identical readings for all slots. I cannot find anything suspicious there.

Pressing on the north bridge while resetting the system has no effect at all. Pressing around the board also seems to have no effect.

I've cleaned a small amount of dirt between the pins of the clock generator and otherwise the board is practically spotless.

I mentioned it earlier in the thread but the floppy drive is also not working. It reports "Floppy Disk(s) fail (C0)"

I'm not sure what else to check.

I wonder how likely it is that the clock generator is faulty, considering that the board is otherwise working. (Just the one memory slot and the floppy drive that have issues, otherwise all good!)

byte_76 wrote on 2025-04-24, 19:28:

Okay so testing each pin of the memory slots from the top gives me near identical readings for all slots. I cannot find anything suspicious there.

It's the same pins on different sockets that should be checked for continuity, not any other way, e.g. pin 2 of slot1 and pin 2 of slot3 (Data 0) and so forth, until all of the data and address bus pins checks out. If there are no problems, then we can conclude that the problem lies somewhere in the control or clock lines. It's a tedious task, but it's the only way to eliminate faulty connections at this moment.

I pulled out my board and checked the clock path to the 1st slot, this is how it's connected to the clock generator IC.

1Clock gen. -> SDRAM
2
318-SD10 -> 42-CK0
417-SD11 -> 125-CK1
537-SD1 -> 79-CK2
638-SD0 -> 163-CK3

Clock gen. and SDRAM slots are separated by series termination resistors in resistor network packages, those resistors are 10 Ohm in value and are marked as "100", see if they are not open.

Regarding the floppy error, if floppy itself and cable are known good, then there might be a problem either with traces that lead to the super I/O chip or super I/O chip's FDC interface is damaged. Set DMM to continuity mode and see if everything is fine in that long trace path, FDC connector should connect directly to that chip. See pages 17-18.

SSTV2 wrote on 2025-04-24, 22:33:

It's the same pins on different sockets that should be checked for continuity, not any other way, e.g. pin 2 of slot1 and pin 2 […]
Show full quote

byte_76 wrote on 2025-04-24, 19:28:

Okay so testing each pin of the memory slots from the top gives me near identical readings for all slots. I cannot find anything suspicious there.

It's the same pins on different sockets that should be checked for continuity, not any other way, e.g. pin 2 of slot1 and pin 2 of slot3 (Data 0) and so forth, until all of the data and address bus pins checks out. If there are no problems, then we can conclude that the problem lies somewhere in the control or clock lines. It's a tedious task, but it's the only way to eliminate faulty connections at this moment.

I pulled out my board and checked the clock path to the 1st slot, this is how it's connected to the clock generator IC.

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1Clock gen. -> SDRAM
2
318-SD10 -> 42-CK0
417-SD11 -> 125-CK1
537-SD1 -> 79-CK2
638-SD0 -> 163-CK3

Clock gen. and SDRAM slots are separated by series termination resistors in resistor network packages, those resistors are 10 Ohm in value and are marked as "100", see if they are not open.

Regarding the floppy error, if floppy itself and cable are known good, then there might be a problem either with traces that lead to the super I/O chip or super I/O chip's FDC interface is damaged. Set DMM to continuity mode and see if everything is fine in that long trace path, FDC connector should connect directly to that chip. See pages 17-18.

Alright, I've done the same measurements to check the path from Memory Slot 1 --> Clock Gen for those 4 pins and in each case, I get a measurement of 10-ohms.

Between each slot, the matching pins numbers have continuity except the following:

1108 nc
2109 nc
3111 /cas
4114 /chip select
5115 /ras
6125 CK1
7129 /s3
8134 nc
9135 nc
10136 nc
11137 nc
12145 nc
13146 vref
14163 /clk
15164 nc
16165 resistance between pins
17166 almost no resistance between slot 1 & 2 but increasing resistance between 2 & 3
18168 VDD
1924 nc
2025 nc
2126 VDD
2228 DQMB1
2342 CK0
2445 Chip Select
2548 Not Used
2650 nc
2751 nc
2861 nc
2962 nc
3079 resistance between pins
3180 nc
3281 nc

I see 2 possible problems:

Pin 28 "DQMB1" must be connected as in the rest of the slots and pin 79 of "CK2", there should be no resistance between the pins, if you get a resistive reading, something is shunting that clock signal. Take a good look at those resistor networks near the clock generator or in between clock generator's legs, residual dirt can create a current path there. What resistance reading do you get there, by the way?

Pin 26 "VDD" should also be connected, but if it's not then don't worry about it, because VDD pins are commonly connected on the RAM module.

Just to be clear, I am measuring between matching PIN numbers of slot 1 and slot2 and again slot 1 and slot 3 and also, just to compare, I'm measuring between slot 2 and slot 3

I've re-checked pins 26 and 28 and confirmed continuity to their matching pins in the other slots. Must have been a bad connection of the leads last time.

Pins 79 causes my multimeter in Auto mode to switch between OL and resistance of around 40 M ohm. It jumps back and forth rapidly. However, on resistance mode, it's OL.

I get 10 ohms on those resistor packs around the Clock Gen.
I've also made absolutely sure that the gaps between the pins of the clock gen are clean.

It seems that all the main signals are connected to the northbridge and are in working order, so now we are left with the control signals and perhaps clock.

I summarised the readings of a DIMM slot for this M/B and measured the voltage drop across control and clock pins (positive DMM probe on ground, negative on pins), see if you get any discrepancies there, it's possible that one of those signals are shunting to ground (blown port in the northbridge).

1Pin 			Description
2
3+1C 	VSS 	Ground
4+2C 	DQ0 	Data 0
5+3C 	DQ1 	Data 1
6+4C 	DQ2 	Data 2
7+5C 	DQ3 	Data 3
8+6C 	VDD 	+3.3 VDC
9+7C 	DQ4 	Data 4
10+8C 	DQ5 	Data 5
11+9C 	DQ6 	Data 6
12+10C 	DQ7 	Data 7
13===
14+11C 	DQ8 	Data 8
15+12C 	VSS 	Ground
16+13C 	DQ9 	Data 9
17+14C 	DQ10 	Data 10
18+15C 	DQ11 	Data 11
19+16C 	DQ12 	Data 12
20+17C 	DQ13 	Data 13
21+18C 	VDD 	+3.3 VDC
22+19C 	DQ14 	Data 14
23+20C 	DQ15 	Data 15
24+21C 	CB0 	Parity/Check Bit Input/Output 0
25+22C 	CB1 	Parity/Check Bit Input/Output 01
26+23C 	VSS 	Ground
27+24 	n/c 	Not connected
28+25 	n/c 	Not connected
29+26C 	VDD 	+3.3 VDC
30?27 	/WE 	Write Enable 600mV
31+28C 	DQMB0 	Byte Mask signal 0
32+29C 	DQMB1 	Byte Mask signal 1
33?30 	/CS0 	Chip Select 0 700mV
34+31C 	DU 		Don't Use
35+32C 	VSS 	Ground
36+33C 	A0 		Address 0
37+34C 	A2 		Address 2
38+35C 	A4 		Address 4
39+36C 	A6 		Address 6
40+37C 	A8 		Address 8
41+38C 	A10/AP 	Address 10
42+39C 	BA1 	Bank Address 1
43+40C 	VDD 	+3.3 VDC
44===
45+41C 	VDD 	+3.3 VDC
46?42 	CK0 	Clock signal 0 690mV
47+43C 	VSS 	Ground
48+44C 	DU 		Don't Use
49?45 	/CS2 	Chip Select 2 710mV
50+46C 	DQMB2 	Byte Mask signal 2
51+47C 	DQMB3 	Byte Mask signal 3
52+48 	DU 		Don't Use
53+49C 	VDD 	+3.3 VDC
54+50 	n/c 	Not connected
55+51 	n/c 	Not connected
56+52C 	CB2 	Parity/Check Bit Input/Output 2
57+53C 	CB3 	Parity/Check Bit Input/Output 3
58+54C 	VSS 	Ground
59+55C 	DQ16 	Data 16
60+56C 	DQ17 	Data 17

61+57C 	DQ18 	Data 18
62+58C 	DQ19 	Data 19
63+59C 	VDD 	+3.3 VDC
64+60C 	DQ20 	Data 20
65+61 	n/c 	Not connected
66+62 	n/c 	Not connected
67+63C 	CKE1 	Clock Enable Signal 1
68+64C 	VSS 	Ground
69+65C 	DQ21 	Data 21
70+66C 	DQ22 	Data 22
71+67C 	DQ23 	Data 23
72+68C 	VSS 	Ground
73+69C 	DQ24 	Data 24
74+70C 	DQ25 	Data 25
75+71C 	DQ26 	Data 26
76+72C 	DQ27 	Data 27
77+73C 	VDD 	+3.3 VDC
78+74C 	DQ28 	Data 28
79+75C 	DQ29 	Data 29
80+76C	DQ30 	Data 30
81+77C 	DQ31 	Data 31
82+78C 	VSS 	Ground
83?79 	CK2 	Clock signal 2 690mV
84+80 	n/c 	Not connected
85+81 	n/c 	Not connected
86+82C 	SDA 	Serial Data
87+83C 	SCL 	Serial Clock
88+84C 	VDD 	+3.3 VDC
89...
90+85C 	VSS 	Ground
91+86C 	DQ32 	Data 32
92+87C 	DQ33 	Data 33
93+88C 	DQ34 	Data 34
94+89C 	DQ35 	Data 35
95+90C 	VDD 	+3.3 VDC
96+91C 	DQ36 	Data 36
97+92C 	DQ37 	Data 37
98+93C 	DQ38 	Data 38
99+94C 	DQ39 	Data 39
100===
101+95C 	DQ40 	Data 40
102+96C 	VSS 	Ground
103+97C 	DQ41 	Data 41
104+98C 	DQ42 	Data 42
105+99C 	DQ43 	Data 43
106+100C 	DQ44 	Data 44
107+101C 	DQ45 	Data 45
108+102C 	VDD 	+3.3 VDC
109+103C 	DQ46 	Data 46
110+104C 	DQ47 	Data 47
111+105C 	CB4 	Parity/Check Bit Input/Output 4
112+106C 	CB5 	Parity/Check Bit Input/Output 5
113+107C 	VSS 	Ground
114+108 	n/c 	Not connected
115+109 	n/c 	Not connected
116+110C 	VDD 	+3.3 VDC
117?111 	/CAS 	Column Address Strobe 600mV
118+112C 	DQMB4 	Byte Mask signal 4
119+113C 	DQMB5 	Byte Mask signal 5
120?114 	/CS1 	Chip Select 1 710
121?115 	/RAS 	Row Address Strobe 600mV
122+116C 	VSS 	Ground
123+117C 	A1 		Address 1
124+118C 	A3 		Address 3
125+119C 	A5 		Address 5
126+120C 	A7  	Address 7
127+121C 	A9 		Address 9
128+122C 	BA0 	Bank Address 0
129+123C 	A11 	Address 11
130+124C 	VDD 	+3.3 VDC
131===
132?125 	CK1 	Clock signal 1 690mV
133+126C 	A12 	Address 12
134+127C 	VSS 	Ground
135+128C 	CKE0 	Clock Enable Signal 0
136?129 	/CS3 	Chip Select 3 710mV
137+130C 	DQMB6 	Byte Mask signal 6
138+131C 	DQMB7 	Byte Mask signal 7
139+132C 	A13 	Address 13
140+133C 	VDD 	+3.3 VDC
141+134 	n/c 	Not connected
142+135 	n/c 	Not connected
143+136 	n/c 	Not connected
144+137 	n/c 	Not connected
145+138C 	VSS 	Ground
146+139C 	DQ48 	Data 48
147+140C 	DQ49 	Data 49
148+141C 	DQ50 	Data 50
149+142C 	DQ51 	Data 51
150+143C 	VDD 	+3.3 VDC
151+144C 	DQ52 	Data 52
152+145 	n/c 	Not connected
153+146 	n/c 	Not connected
154+147 	n/c 	Not connected
155+148C 	VSS 	Ground
156+149C 	DQ53 	Data 53
157+150C 	DQ54 	Data 54
158+151C 	DQ55 	Data 55
159+152C 	VSS 	Ground
160+153C 	DQ56 	Data 56
161+154C 	DQ57 	Data 57
162+155C 	DQ58 	Data 58
163+156C 	DQ59 	Data 59
164+157C 	VDD 	+3.3 VDC
165+158C 	DQ60 	Data 60
166+159C 	DQ61 	Data 61
167+160C 	DQ62 	Data 62
168+161C 	DQ63 	Data 63
169+162C 	VSS 	Ground
170?163 	CK3 	Clock signal 3 690mV
171+164 	n/c 	Not connected
172+165 	SA0 	Serial address 0
173+166 	SA1 	Serial address 1
174+167 	SA2 	Serial address 2
175+168 	VDD 	+3.3 VDC
176
177Serial addresses are hardwired to VSS or VDD for each slot specifically.

The "+" here means that this pin is OK, "C" means continuity between the same pins on different slots, "?" - focus your attention on these now. Voltage drop readings obtained using diode mode.

SSTV2 wrote on 2025-04-26, 13:25:

It seems that all the main signals are connected to the northbridge and are in working order, so now we are left with the contro […]
Show full quote

It seems that all the main signals are connected to the northbridge and are in working order, so now we are left with the control signals and perhaps clock.

I summarised the readings of a DIMM slot for this M/B and measured the voltage drop across control and clock pins (positive DMM probe on ground, negative on pins), see if you get any discrepancies there, it's possible that one of those signals are shunting to ground (blown port in the northbridge).

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1Pin 			Description
2
3+1C 	VSS 	Ground
4+2C 	DQ0 	Data 0
5+3C 	DQ1 	Data 1
6+4C 	DQ2 	Data 2
7+5C 	DQ3 	Data 3
8+6C 	VDD 	+3.3 VDC
9+7C 	DQ4 	Data 4
10+8C 	DQ5 	Data 5
11+9C 	DQ6 	Data 6
12+10C 	DQ7 	Data 7
13===
14+11C 	DQ8 	Data 8
15+12C 	VSS 	Ground
16+13C 	DQ9 	Data 9
17+14C 	DQ10 	Data 10
18+15C 	DQ11 	Data 11
19+16C 	DQ12 	Data 12
20+17C 	DQ13 	Data 13
21+18C 	VDD 	+3.3 VDC
22+19C 	DQ14 	Data 14
23+20C 	DQ15 	Data 15
24+21C 	CB0 	Parity/Check Bit Input/Output 0
25+22C 	CB1 	Parity/Check Bit Input/Output 01
26+23C 	VSS 	Ground
27+24 	n/c 	Not connected
28+25 	n/c 	Not connected
29+26C 	VDD 	+3.3 VDC
30?27 	/WE 	Write Enable 600mV
31+28C 	DQMB0 	Byte Mask signal 0
32+29C 	DQMB1 	Byte Mask signal 1
33?30 	/CS0 	Chip Select 0 700mV
34+31C 	DU 		Don't Use
35+32C 	VSS 	Ground
36+33C 	A0 		Address 0
37+34C 	A2 		Address 2
38+35C 	A4 		Address 4
39+36C 	A6 		Address 6
40+37C 	A8 		Address 8
41+38C 	A10/AP 	Address 10
42+39C 	BA1 	Bank Address 1
43+40C 	VDD 	+3.3 VDC
44===
45+41C 	VDD 	+3.3 VDC
46?42 	CK0 	Clock signal 0 690mV
47+43C 	VSS 	Ground
48+44C 	DU 		Don't Use
49?45 	/CS2 	Chip Select 2 710mV
50+46C 	DQMB2 	Byte Mask signal 2
51+47C 	DQMB3 	Byte Mask signal 3
52+48 	DU 		Don't Use
53+49C 	VDD 	+3.3 VDC
54+50 	n/c 	Not connected
55+51 	n/c 	Not connected
56+52C 	CB2 	Parity/Check Bit Input/Output 2
57+53C 	CB3 	Parity/Check Bit Input/Output 3
58+54C 	VSS 	Ground
59+55C 	DQ16 	Data 16
60+56C 	DQ17 	Data 17

…Show last 117 lines

61+57C 	DQ18 	Data 18
62+58C 	DQ19 	Data 19
63+59C 	VDD 	+3.3 VDC
64+60C 	DQ20 	Data 20
65+61 	n/c 	Not connected
66+62 	n/c 	Not connected
67+63C 	CKE1 	Clock Enable Signal 1
68+64C 	VSS 	Ground
69+65C 	DQ21 	Data 21
70+66C 	DQ22 	Data 22
71+67C 	DQ23 	Data 23
72+68C 	VSS 	Ground
73+69C 	DQ24 	Data 24
74+70C 	DQ25 	Data 25
75+71C 	DQ26 	Data 26
76+72C 	DQ27 	Data 27
77+73C 	VDD 	+3.3 VDC
78+74C 	DQ28 	Data 28
79+75C 	DQ29 	Data 29
80+76C	DQ30 	Data 30
81+77C 	DQ31 	Data 31
82+78C 	VSS 	Ground
83?79 	CK2 	Clock signal 2 690mV
84+80 	n/c 	Not connected
85+81 	n/c 	Not connected
86+82C 	SDA 	Serial Data
87+83C 	SCL 	Serial Clock
88+84C 	VDD 	+3.3 VDC
89...
90+85C 	VSS 	Ground
91+86C 	DQ32 	Data 32
92+87C 	DQ33 	Data 33
93+88C 	DQ34 	Data 34
94+89C 	DQ35 	Data 35
95+90C 	VDD 	+3.3 VDC
96+91C 	DQ36 	Data 36
97+92C 	DQ37 	Data 37
98+93C 	DQ38 	Data 38
99+94C 	DQ39 	Data 39
100===
101+95C 	DQ40 	Data 40
102+96C 	VSS 	Ground
103+97C 	DQ41 	Data 41
104+98C 	DQ42 	Data 42
105+99C 	DQ43 	Data 43
106+100C 	DQ44 	Data 44
107+101C 	DQ45 	Data 45
108+102C 	VDD 	+3.3 VDC
109+103C 	DQ46 	Data 46
110+104C 	DQ47 	Data 47
111+105C 	CB4 	Parity/Check Bit Input/Output 4
112+106C 	CB5 	Parity/Check Bit Input/Output 5
113+107C 	VSS 	Ground
114+108 	n/c 	Not connected
115+109 	n/c 	Not connected
116+110C 	VDD 	+3.3 VDC
117?111 	/CAS 	Column Address Strobe 600mV
118+112C 	DQMB4 	Byte Mask signal 4
119+113C 	DQMB5 	Byte Mask signal 5
120?114 	/CS1 	Chip Select 1 710
121?115 	/RAS 	Row Address Strobe 600mV
122+116C 	VSS 	Ground
123+117C 	A1 		Address 1
124+118C 	A3 		Address 3
125+119C 	A5 		Address 5
126+120C 	A7  	Address 7
127+121C 	A9 		Address 9
128+122C 	BA0 	Bank Address 0
129+123C 	A11 	Address 11
130+124C 	VDD 	+3.3 VDC
131===
132?125 	CK1 	Clock signal 1 690mV
133+126C 	A12 	Address 12
134+127C 	VSS 	Ground
135+128C 	CKE0 	Clock Enable Signal 0
136?129 	/CS3 	Chip Select 3 710mV
137+130C 	DQMB6 	Byte Mask signal 6
138+131C 	DQMB7 	Byte Mask signal 7
139+132C 	A13 	Address 13
140+133C 	VDD 	+3.3 VDC
141+134 	n/c 	Not connected
142+135 	n/c 	Not connected
143+136 	n/c 	Not connected
144+137 	n/c 	Not connected
145+138C 	VSS 	Ground
146+139C 	DQ48 	Data 48
147+140C 	DQ49 	Data 49
148+141C 	DQ50 	Data 50
149+142C 	DQ51 	Data 51
150+143C 	VDD 	+3.3 VDC
151+144C 	DQ52 	Data 52
152+145 	n/c 	Not connected
153+146 	n/c 	Not connected
154+147 	n/c 	Not connected
155+148C 	VSS 	Ground
156+149C 	DQ53 	Data 53
157+150C 	DQ54 	Data 54
158+151C 	DQ55 	Data 55
159+152C 	VSS 	Ground
160+153C 	DQ56 	Data 56
161+154C 	DQ57 	Data 57
162+155C 	DQ58 	Data 58
163+156C 	DQ59 	Data 59
164+157C 	VDD 	+3.3 VDC
165+158C 	DQ60 	Data 60
166+159C 	DQ61 	Data 61
167+160C 	DQ62 	Data 62
168+161C 	DQ63 	Data 63
169+162C 	VSS 	Ground
170?163 	CK3 	Clock signal 3 690mV
171+164 	n/c 	Not connected
172+165 	SA0 	Serial address 0
173+166 	SA1 	Serial address 1
174+167 	SA2 	Serial address 2
175+168 	VDD 	+3.3 VDC
176
177Serial addresses are hardwired to VSS or VDD for each slot specifically.

The "+" here means that this pin is OK, "C" means continuity between the same pins on different slots, "?" - focus your attention on these now. Voltage drop readings obtained using diode mode.

I'm not sure if I understood you correctly but here's my feedback:

I put my multimeter into diode mode and connected the positive lead to the ground on one of the molex connectors.

Using the negative lead, I measured the pins that you marked with a question mark and I got these readings:

Unless otherwise stated, the readings were consistent on same pins across the 3 slots

27 0.0v
30 0.0v
42 0.500v (0.0v on slots 2 & 3)
45 0.0v
79 0.0v
111 0.555
114 0.0v
115 0.555v
125 0.529 (0.0v on slots 2 & 3)
129 -3.473
163 1.773v.

Strange readings, the motherboard was off, right?

Yes, sorry, I assumed we needed power to measure voltage.
I have very little experience with electronics so really just doing this blindly without understanding what we’re doing.

I’ll take those measurements again today after work.