No, I don't think so, I only picked it up again because I ran into your question. Do I have to ?

Those 4 are not in my file because they are not FCPGA.

Ran into a photo of SL49H that shows it's a cB0 stepping.
https://www.cpu-galaxy.at/cpu/intel%20cpu/pen … i%20section.htm

red-ray wrote on 2025-05-07, 05:26:

PC Hoarder Patrol wrote on 2025-05-07, 04:42:

Finally got round to the promised check!...

Thank you it's [cB0] as I suspected it would be and not [cD0], the images also confirm the year as 2000.

I wonder why SIV didn't report much for GPU-1 + GPU-2, what are they please? What does Menu->Machine->GPU Info report? At a guess Voodoo 1 or 2.

Sorry, that one's on me...this was a clean XP install on a test rig and I didn't bother with video drivers (S3 Trio3D/2X)...fixed now (note cpus have been restored to their normal 2 x SL5QV)

PC Hoarder Patrol wrote on 2025-05-08, 11:18:

I didn't bother with video drivers (S3 Trio3D/2X)

Thank you and mystery solved, as you had not installed the drivers Plan A did not find any GPUs so SIV moved onto Plan B which did, Plan A filters out NetMeeting + RDPDD and I guess I should adjust Plan B to do the same, then again having them there is harmless.

I just looked up SL5QV in the SIV S-Spec table and it seems to be the only stepping cD0 that does 10 x 100 MHz, is it or if my table missing an entry? SIV 5.81 Beta-06 may report @ SL5QV and Beta-07 should.

PARKE wrote on 2025-05-08, 10:45:

Ran into a photo of SL49H that shows it's a cB0 stepping.

OK, but what am I missing, from the image I can't see any indication it's cB0 stepping.

cD0 has typically a new front layout and the rear is different too; it was a more drastic stepping upgrade than the earlier one. Here an example of two of my own chips:

The cD0 in the photo is technically superior too, it runs at fsb 133/1.13GHz with stock voltage.

PARKE wrote on 2025-05-08, 13:43:

Here an example of two of my own chips:

Thank you, so to do this you keen to know what the chips from each stepping look like, I don't.

It helps in some cases. But we could f.e not tell the difference between a cB0 and a cC0 from looks.

PARKE wrote on 2025-05-08, 15:16:

It helps in some cases. But we could f.e not tell the difference between a cB0 and a cC0 from looks.

I feel I would like to read the CPUID to be 100% sure.

I was looking at you overclocked SL4Z2 and wondering if SIV will report it as a SL4Z2, please will you try SIV V5.81 Beta-07 and let me know. You need to use the beta as the 5.80 release does not have any Coppermine stepping information. If it doesn't you could do Menu->File->Save Local and post/pm/e-mail me the two save files so I can fix it for Beta-08.

Will try this weekend.

PARKE wrote on 2025-05-09, 14:48:

Will try this weekend.

Great, I have just released SIV V5.81 Beta-07 so please it that.

Here you go:

PARKE wrote on 2025-05-10, 09:02:

Here you go:

Thank you, SIV32O.exe is a special build for Windows NT V3.51 and the screen is expected to be messed up on NT V4.00 and later + Windows 9x/Me. Below is which systems all the different SIV builds should work on.

I had assumed you would be running Windows XP on the P-!!!, SIV needs to read some MSRs to correctly report your CPU and can only so this on Windows NT/XP and later. I decided not to develop a VXD as Windows 9x does not support Structured Exception Handling in VXDs so if SIV tried to read an MSR that did not exist you would get a BSOD.

1. SIV32O.exe (ASCII) - Windows NT V3.51 only
2. SIV32L.exe (ASCII) - Windows 9x/Me, NT V4.00 and later or Windows NT V3.51 with newshell2 installed.
3. SIV32N.exe (Unicode) - Windows NT V4.00 and later
4. SIV32X.exe (Unicode) - Windows 2000 V5.00 and later
5. SIV64X.exe (Unicode) - Windows XP-64 V5.02 and later
6. SIV32A.exe (Unicode) - Windows on DEC Alpha
7. SIV64I.exe (Unicode) - Windows on Intel Itanium

Sorry, but I don't think this cpu is going to be combined with an XP system anytime soon. It sits in my oldest system with a 13GB IBM hd and I do not have much luck with fiddleing lately.

Also for entertainment:
after substantial digging I have been unable to find any evidence of real life existence of the
S-Specs below. Some of the reasons may be that they were announced via bulletins by Intel
but never actually released or that they occured in early Intel Specification Updates but were
later omitted. Also human error cannot be ruled out. Cpu-World has existed since early 2000 and
it is not clear what the info source for some of the entries was.
Comments and corrections are welcome.

(nf means not found)
1 -SL2PV nf
2 -SL2QD nf
3 -SL2QE nf error ?
4 -SL2X2 nf
5 -SL3KZ nf listed as Coppermine by Chris Hare - see Ars Technica
6 -SL3US nf the only cA0 stepping ? - was it released ?
7 -SL46R nf SL4.. is out of sync with this CPUID - see Ars Technica
8 -SL532 nf
9 -SL5E6 nf SL5.. is out of sync with this CPUID
10 -SL5EA nf not released - see Chris Hare
11 -SL5HG nf
12 -SL5HH nf
13 -SL5HK nf listed as FCPGA2 at CPUW
14 -SL5HL nf
15 -SL5L7 nf
16 -SL65C nf wrong S-Spec - SL6.. a-typical for this product
17 -SL6BZ nf not released
18 -SL6C2 nf not released
19 -SL6C3 nf not released
20 -SL6C4 nf not released
21 -SL6HR nf
22 -SL6HS nf
23 -SL6TG nf mobile cpu PGA495/BGA495
24 -SL6TH nf mobile cpu PGA495/BGA495

PARKE wrote on 2025-05-17, 11:48:

6 -SL3US nf the only cA0 stepping ? - was it released ?

Thank you for the information, SIV did not have cA0 as a possible stepping in SIV so added it "just-in-case".

SIV does have the Coppermine stepping 4 as cB1, but not any S-Specs for this.

I guess you have updated your database with this information, please may I have a new .TSV file?

The cA0 S-Spec comes from CPUW:
https://www.cpu-world.com/sspec/SL/SL3US.html

The steppings with [B1] that I have are:
B1 06B4h Tualeron Tualatin-256
dB1 0653h Deschutes
tB1 06B4h Tualatin
tB1 06B4h Tualatin S

The problem cases are still in the file with [-} in front of the S-Spec because I want to keep track on what I have done. But I can send any output that you want.

Thank you, I should have been clearer and specified "SIV does have the Coppermine stepping 4 as cB1, but not any S-Specs for this.", given it cB1 to me it's clearly Coppermine.

The same as the previous .TSV you sent would be good, SIV already has code to deal with and report the anomalies.

The CPUID for the cA0 SL3US must be 0860 given cA2 is 0681. You could also fill in some of the other CPUIDs given the cD0 they will be 068A, etc..

Which entry do you have for a cB1 stepping ? As far as I can see the Coppermine progressed from cB0 to cCo.
This is how it looks here:
B0 Celeron Coppermine-128
C0 Celeron Coppermine-128
D0 Celeron Coppermine-128
cA2 Coppermine
cA2 Coppermine slot 1
cB0 Coppermine
cB0 Coppermine slot 1
cC0 Coppermine
cC0 Coppermine slot 1
cD0 Coppermine
cD0 Coppermine-T

I think I never entered additional (missing) info on CPUID etc. unless I found hard evidence but you can do that if you need it for SIV of course - I wanted to stay as close as possible to the 'official' Intel data.

Do you want an output with or without the questionable entries ?

PARKE wrote on 2025-05-17, 13:46:

Which entry do you have for a cB1 stepping ? As far as I can see the Coppermine progressed from cB0 to cCo.

I think I never entered additional (missing) info on CPUID etc. unless I found hard evidence but you can do that if you need it for SIV of course - I wanted to stay as close as possible to the 'official' Intel data.

Do you want an output with or without the questionable entries ?

As I said I don't have any S-Specs, just an entry in the code that translates from stepping number to stepping designation.

That's your call, by definition if it's cDo it will be CPUID 068A

With the questionable entries please.

1      switch( cpu->model * 0x10 + cpu->stepping )                               //
2      {                                                                         //
3        case 0x80: cpu->step = TEXT( " [cA0]" );                    break;      //  CPU Stepping
4        case 0x81: cpu->step = TEXT( " [cA2]" );                    break;      //
5        case 0x83: cpu->step = TEXT( " [cB0]" );                    break;      //
6        case 0x84: cpu->step = TEXT( " [cB1]" );                    break;      // I can't find any S-Specs for this
7        case 0x86: cpu->step = TEXT( " [cC0]" );                    break;      //
8        case 0x8A: cpu->step = TEXT( " [cD0]" );                    break;      //
9      }                                                                         //