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Anomalies in the Intel® Processor Specification Updates

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Reply 120 of 147, by PARKE

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This should work.

The attachment SIV30-5.txt is no longer available

There is a part with missing CPUID & source info because I cannot find
Mobile Intel® Pentium® 4 Processor-M Specification Update
document: 250721-037

Reply 121 of 147, by red-ray

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PARKE wrote on 2025-05-29, 23:47:

This should work.

Thank you and after a few small tweaks SIV did OK. SIV skipped 720 as it does as yet not have them in it's table.

file.php?id=220574

I noted as below, if you fix these or other issues please may I have a new file.

  1. SL6QU had Ghz, all the others have GHz
  2. All the Pentium 2 Xeon have Drake missing
  3. All Pentium III Xeon CPUID 067n are Tanner, you have some as Cascades.
  4. Xeon CPUID 0F0n + 0F1n are Foster
  5. Xeon CPUID 0F2n are Prestonia or Gallatin (L3 cache)
  6. The 4 missing from your file are all on CPU World.
  7. I plan to add Xeon Foster + Prestonia + Gallatin to SIV.

Reply 122 of 147, by PARKE

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Thanks for the output and the additional info on type names.

Updated the missing stuff.

The 6 Tanners with question marks are 0672 according to Intel.

you:[The 4 missing from your file are all on CPU World.] Not sure which 4 you refer to.

The attachment SIV305-2.txt is no longer available

Reply 123 of 147, by red-ray

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PARKE wrote on 2025-05-30, 11:48:

you:[The 4 missing from your file are all on CPU World.] Not sure which 4 you refer to.

Thank for for the updated file, SIV now reports as below.

file.php?id=220589

  1. All the Xeon-nnnn are because Foster/Gallatin is missing for those CPUs.
  2. The 4 missing are the last 4 listed, they are in the SIV tables, but missing you your file.
  3. You don't have the CPUID for SL3US
  4. You don't save the Stepping for SL46R

Update 1: You also need to add SL7RR, see https://www.cpu-world.com/sspec/SL/SL7RR.html
Update 2: P4 90nm is Prescott

Last edited by red-ray on 2025-05-31, 06:32. Edited 1 time in total.

Reply 124 of 147, by red-ray

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I have just added Banias + Dothan and wonder, why their stepping's contain -? CPU World does not show a -.

file.php?id=220618

Reply 125 of 147, by PARKE

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These entries come straight from the Intel sheets. I guess it is a matter of taste if one follows the CPU world methodology or not. There are more coming like that and it looks as if Intel started a new alphabet format:
A-0 0F41h
A-1 10011b
B-0 0F49H
B-1 0695h
B-1 06D6h
B-2 06F6h
C-0 06D8h
C-0 06E8H
C-0 06E8h
D-0 06ECh
D-0 0F34h
E-0 0F41h
G-1 0F49h
N-0 0F43h
R-0 0F4Ah

Reply 126 of 147, by red-ray

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PARKE wrote on 2025-05-31, 00:15:

These entries come straight from the Intel sheets. I guess it is a matter of taste if one follows the CPU world methodology or not.

It seems to be a phase they went through, to me it looks like later CPUs don't have the -.

file.php?id=220624

It's easy enough for to to get SIV to lose the - and use a consistent form. May I have the latest file please?, hopefully with it some of the whinges will go away. I added Smithfield + Nocona + Irwindale + Paxville as they are the same vintage as Prescott.

file.php?id=220635

Reply 127 of 147, by PARKE

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Yes, Intel seems not to worry about inconsistancies in its bookkeeping. Both with - and without keep occuring up to where I am now at.
Here is the last update.
We could of course avoid some +/-20 'issues' reoccuring by just deleting those CPUW crantasy listings. Dozens of worldwide enthousiast volunteers have over the years added to that database and it is extremely unlikely that no errors were made. 20 out of 1.500 is imo even below what I would expect to see as a result of human error. It is a waste of time trying to find provenance for a handful of listings of chips that maybe never made it into the wild - it is for me anyway.

The attachment SIV31-5.txt is no longer available

Reply 128 of 147, by red-ray

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PARKE wrote on 2025-05-31, 10:11:

Here is the last update.
We could of course avoid some +/-20 'issues' reoccuring

Thank you for this update, SIV does not count Unknown - issue typo reports as issues, it simply reports them. With the latest you could/should fix:

  1. The 15 from SL66Z should be Gallatin as they have L3 cache, further CPU World says Gallatin, see https://www.cpu-world.com/sspec/SL/SL66Z.html
  2. Cranford-3666 [B0] SL84UN is a typo, it should be SL8UN
  3. SL46R is stepping B0, see https://www.cpu-world.com/sspec/SL/SL46R.html
  4. SL3US must be CPUID 0680, it's the only option.
  5. SL9BN is missing, it Stepping C0 CPUID 06E8, see download/file.php?id=220668
  6. P4 90nm is Prescott
  7. Pentium D800 is Smithfield
  8. 64-bit Xeon MP is Cranford
  9. Xeon 64bits + 2M L2 is Irwindale
  10. Xeon 64bits + 1M L2 is Nocona
  11. Pentium 4 6x1 is Cedar Mill
  12. Pentium D 900 is Presler
  13. Core Duo/Solo is Yonah
  14. From SL4U3 are 15 that SIV has and are missing from your file. They are all on CPU World.

file.php?id=220662

Reply 129 of 147, by PARKE

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The last version.
Your comments in the last message are now dealt with, I think.
The last line puzzles me a bit:
[From SL4U3 are 15 that SIV has and are missing from your file. They are all on CPU World.]
Which 15 do you refer to ?

The attachment SIV01-6.txt is no longer available

Reply 130 of 147, by red-ray

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PARKE wrote on 2025-06-01, 10:49:

The last line puzzles me a bit: [From SL4U3 are 15 that SIV has and are missing from your file. They are all on CPU World.] Which 15 do you refer to ?

Thank you for the updated file, there are now just two issues:

  1. SL3US must be CPUID 0680, it's the only option.
  2. SL7RR is 3.40 GHz, not 3.50GHz, see https://www.cpu-world.com/sspec/SL/SL7RR.html

There are now 42 missing from your file that SIV has, the first is QHF3QS and the last one is SLA67

Their S-Specs are QHF3QS SL92C SL99U SL99T SL92U SL92W SL9BN SL9LA SL9LB SL9LC SL8ED SL8EW SL8EY SL7ZG SL8ZR SL7ZQ SL8ZP SL943 SL7ZK SL7ZJ SL7ZB SL8UA SL8UB SL8MA QHBBES SL8UC SL8UD SL9QA SL9Q9 SL9HF SL9HC SL9HE SL9HB SL9HD SL9HA SL9YR SLA6A SLA69 SLA77 SLA6B SLA68 SLA67

red-ray wrote on 2025-05-31, 12:00:
  1. Pentium D800 is Smithfield
  2. Core Duo/Solo is Yonah

It looks like you missed these two.

Update: SLACP is CPUID 06FB, not 06F7, see https://www.cpu-world.com/sspec/SL/SLACP.html
Core 2 Duo CPUID 06Fn is Conroe
Xeon Processor 5100 Series is Woodcrest
Xeon Processor 5300 Series is Clovertown, but you don't seem to have them.
Xeon Processor 3300 Series is Yorkfield

CPUID and Speed are interposed for all Xeon Processor 3300 Series
SLAN5		C0	2.83GHz/1333	10676h	Xeon Processor 3300 Series	12MB(2x6MB)				775-land-LGA
SLAN7 C0 2.66GHz/1333 10676h Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLAWF M1 2.50GHz/1333 10676h Xeon Processor 3300 Series 6MB(2x3MB) 775-land-LGA
SLAWZ C1 2.83GHz/1333 10676h Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLAX2 C1 2.66GHz/1333 10676h Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLB69 R0 2.50GHz/1333 1067Ah Xeon Processor 3300 Series 6MB(2x3MB) 775-land-LGA
SLB6C R0 2.66GHz/1333 1067Ah Xeon Processor 3300 Series 6MB(2x3MB) 775-land-LGA
SLB8X E0 2.83GHz/1333 1067Ah Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLB8Y E0 2.66GHz/1333 1067Ah Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLB8Z E0 3.00GHz/1333 1067Ah Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLGPF E0 2.83GHz/1333 1067Ah Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA
SLGPG E0 3.16GHz/1333 1067Ah Xeon Processor 3300 Series 12MB(2x6MB) 775-land-LGA

file.php?id=220742

Last edited by red-ray on 2025-06-01, 15:08. Edited 1 time in total.

Reply 131 of 147, by PARKE

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red-ray wrote on 2025-06-01, 11:51:

There are now 42 missing from your file that SIV has

Do you have the sheets where these came from ?
The last Xeons look like Tigertons and should be in:
Intel Xeon Processor 7200 and 7300 Series Specification Update / Intel 318081

Reply 133 of 147, by red-ray

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PARKE wrote on 2025-06-01, 15:04:

Do you have the sheets where these came from ?

No, I got most of them from CPU World

Reply 134 of 147, by red-ray

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In your file there is:

SLAPK		C0	10676h	3.16GHz/1333MHz	Core 2 Duo	6MB(2x3MB)				775-land-LGA	
SLAPL C0 10676h 3.00GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLAPN C0 10676h 2.83GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLAPP C0 10676h 2.66GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLAQR C0 10676h 2.66GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLB9J E0 1067Ah 3.00GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLB9K E0 1067Ah 3.16GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA
SLB9L E0 1067Ah 3.33GHz/1333MHz Core 2 Duo 6MB(2x3MB) 775-land-LGA

No Core 2 Duo have 2 x L2 cache below is a SLB9K it has 1 x 6MB that is shared by both cores. Where did this incorrect information come from?

I also noted that the size is sometimes 4M and other times 4MB, etc.. Were it my file I would be consistent. SIV always used M or K.

BTW all Core 2 Duo CPUID 1067n are Wolfdale and Core 2 Quad CPUID 1067n are Yorkfield

file.php?id=220766

Reply 135 of 147, by PARKE

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red-ray wrote on 2025-06-01, 20:54:

No Core 2 Duo have 2 x L2 cache below is a SLB9K it has 1 x 6MB that is shared by both cores. Where did this incorrect information come from?
I also noted that the size is sometimes 4M and other times 4MB, etc.. Were it my file I would be consistent. SIV always used M or K.

Don't shoot the messenger. Except when mentioned otherwise in the column [source2] everything comes directly from the Intel spec sheets. I do no type anything, it is all copy>paste entire sets of pages and some format editing when necessary plus redirecting the data to fields in a database table.
For the 6MB/2x3MB see page 16:

The attachment 31873320.pdf is no longer available

The other stuff will all be fixed in due time.

Reply 136 of 147, by red-ray

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red-ray wrote on 2025-06-01, 20:54:

Where did this incorrect information come from?

PARKE wrote on 2025-06-01, 21:52:

Don't shoot the messenger.

I didn't, I correctly assumed the information was another class of anomaly and made you aware of it.

SLB5W		R0	1067Ah	2.5GHz/1333MHz	Core 2 Quad	4MB(2x3MB)				775-land-LGA
SLGT6 R0 1067Ah 2.66GHz/1333MHz Core 2 Quad Yorkfield 4MB(2x3MB) 775-land-LGA
SLGT7 R0 1067Ah 2.66GHz/1333MHz Core 2 Quad 4MB(2x3MB) 775-land-LGA
SLGUR R0 1067Ah 2.5GHz/1333MHz Core 2 Quad 4MB(2x3MB) 775-land-LGA

Another anomaly is that I guess Intel think 4MB = 2x3MB, why don't they all specify Yorkfield ?

file.php?id=220776

Having added L2/L3 cache size checks there are now 16 issues. There are also 59 with No L2 cache information at all.

I think SLARW is a typo as SLAWR is a Yorkfield-2666 and Google can't find SLARW.

I suspect SL4D3 + SL4D4 + SL4D5 are typos on https://www.pchardwarelinks.com/remark.htm, that seems to be the only place they exist and they should be SL5D3 + SL5D4 + SL5D5.

Reply 137 of 147, by red-ray

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In the Intel S-Spec update the CPUIDs for SLAWF + SLAX2 + SLAWZ are incorrect, they should all be CPUID 10677.

I have a SLAWF and below proves this, the other 2 are stepping C1 and the Intel Core 2 Quad stepping C1 are CPUID 10677 so they also look to be incorrect.

file.php?id=220804

Reply 138 of 147, by red-ray

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Dual Core Xeon LV is Sossaman
Intel Xeon 5000 Series is Dempsey
Intel Xeon 5400 Series is Harpertown

Reply 139 of 147, by PARKE

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More streamlined:

The attachment SIV02-6.txt is no longer available