Reply 180 of 220, by red-ray
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PARKE wrote on 2025-06-14, 09:14:Do mobile chips with the same CPUID come with the same nomenclature ?
Often, but it would be wise to check what CPU World and/or Wikipedia says.
PARKE wrote on 2025-06-14, 09:14:Do mobile chips with the same CPUID come with the same nomenclature ?
Often, but it would be wise to check what CPU World and/or Wikipedia says.
I added all the P4 Celerons and noted:
In my opinion some are accidentally entered two times by the people who typed the data or one of the two identical S-Specs is incorrect and some may actually have been produced with identical S-Specs - like for example the PII SECC you are discussing. The jury is still out for that one imo.
PARKE wrote on 2025-06-14, 13:34:The jury is still out for that one imo.
OK, I have been adding P4 Mobile.
Thanks for all the additional names. The Mobile P4 90-nm from pdf 302441 is later and supports hyper-threading.
PARKE wrote on 2025-06-14, 15:26:The Mobile P4 90-nm from pdf 302441 is later and supports hyper-threading.
OK, however I was really asking, why do the two Northwoods have very different names? Looking further one is Mobile P4 533MHz fsb
Also I noted below, given the 400MHz FSB then 2.33 GHz is impossible and https://www.cpu-world.com/sspec/SL/SL789.html says 2.30 GHz.
SL789 checked D1 0F29h 2.33GHz/400MHz Mobile Pentium 4-M 512KB sep 2002 35 1.3 400 2333.00 23 RK80532GC052512SL789 Malay
I have added more and noted:
red-ray wrote on 2025-06-14, 18:39:OK, however I was really asking, why do the two Northwoods have very different names? Looking further one is Mobile P4 533MHz fsb
Also I noted below, given the 400MHz FSB then 2.33 GHz is impossible
Yes, I sensed that you were asking that. The plan was to first import data from the available Intel sheets and weed trough the crop in the later phase. These headers derive from the sheets and I made them just to be able to sort the different categories and relate to the original specsheets - using just numbers doesn't work for me. Two weeks ago I had no idea that all those Intel cpu's had their own name. I have now changed all the P4's into Pentium 4
The 2.33GHZ is my fault, happened during individual/manual import.
Do you have the CPUID for Xeon L3406 ?
PARKE wrote on 2025-06-15, 10:24:Do you have the CPUID for Xeon L3406 ?
https://www.cpu-world.com/CPUs/Xeon/Int ... 3406).html says 20652, it's also says it's Clarkdale, SIV has:
SLBRX 020652 Clarkdale
SLBQQ 020652 Clarkdale
SLBT9 020655 Clarkdale
SLBT8 020655 Clarkdale
In general once you know the codename and stepping you can lookup the Signature/CPUID in the [ Windows CPU µCode Updates ] (Menu->Hardware->BIOS Tables->Windows CPU µCode) panel.
As far as I can tell SL9WN is CPUID 010661, https://www.cpu-world.com/sspec/SL/SL9WN.html does not list a CPUID, but https://www.cpu-world.com/sspec/SL/SLA2G.html lists 010661, I just found a SIV save from an Intel Celeron M 520 (Merom) CPUID 010661 and looking at https://en.wikipedia.org/wiki/List_of_I ... ge,_65_nm) there are only two possible and SL9WT is CPUID 0006F6.
This is the one with 10011b in the s-spec update.
Dual-Core Mobile 65-nm + CPUID 06En should have Yonah
Dual-Core Mobile 65-nm + CPUID 06Fn should have Merom
Mobile Celeron Dual-Core should have Merom
As below are missing and when do you plan to have a new .TSV file please?
0006FD, Merom-1866, SLA4H, M0
0006FD, Merom-2000, SLA4G, M0
0006FD, Merom-2000, SLAVG, M0
0006FD, Merom-2166, SLB3P, M0
0006FD, Merom-1866, SLAQK, M0
Thanks for the additional info. Here is a new one - still under construction.
PARKE wrote on 2025-06-16, 21:01:Here is a new one
Thank you, lots of changes! Most of the issues are clear enough from the screen shot and most are the L3 cache size missing. Please may I have 32305602.pdf for the SLBQK data.
SLB5G E0 01067Ah 2.27GHz/1066MHz Core 2 Mobile 12MB m-FCPGA
SLB5J E0 01067Ah 2.53GHz/1066MHz Core 2 Mobile 12MB m-FCPGA
SLB5G E0 01067Ah 2.27GHz/1066MHz Core 2 Mobile Penryn-QC 2 x 6MB m-FCPGA
SLB5J E0 01067Ah 2.53GHz/1066MHz Core 2 Mobile Penryn-QC 2 x 6MB m-FCPGA
I checked all the Lynnfield speeds @ CPU World and it reports the SIV numbers.
Beckton had Ghz rather than GHz, I enabled SIV fixup so the L3 cache issues were reported.
Mobile Celeron 266MHz-466MHz should have Mendocino.
Mobile Pentium III-M should have Tualatin.
Mobile Pentium 4 90-nm should have Prescott
Mobile Pentium 4 533MHz fsb should have Prescott
Core 2 Duo 965 Extreme should have Merom.
SIV has SL4G7, I feel you should change SL4G7(2) to SL4G7 and SL4G7(1) to SL4G7(2)
Sandy Bridge is a totally different CPU to Sandy Bridge-E, same for Ivy Bridge + Haswell + Broadwell + Sky Lake.
Given this Sandy Bridge should often be Sandy Bridge-EN or Sandy Bridge-EP, see https://en.wikipedia.org/wiki/List_of_I ... erformance
The cache information is absent from all the Sandy Bridge + Sandy Bridge-E + Ivy Bridge !
All these missing cache sizes mean other issues may be missed.
Again thanks for all the corrections. The Lynnfield errors were the result of starting with Wiki info which I got mixed up - the Intel sheet is correct but I did not check them against each other yet.
The 323056 specification update does not contain info on any individual cpu. The SLBQK reference came from some release article and this cpu should/could have occured in that sheet. The four related S-Specs/model numbers come from Wiki.
There is no L3 info in the L2 column anymore because I do not like the convoluted look - I made a separate column for L3. I also made a separate column for model numbers but because your c-construct is fit for the format that we agreed on I left them out. Columns that are not used for later products (like 'Mfg' and ' tag ram' could be used as substitutes - just let me know how you want it.
One question, how do I distinguish f.e. the single 2MB cache from the 2 x 1MB cache types.
ps I also made separate columns for the DDR3 and QPI info but I must say that I seriously doubt that I am going to venture into later generations; most of the ' modern' info is above my head and it does not really interest me.
PARKE wrote on 2025-06-17, 11:41:There is no L3 info in the L2 column anymore because I do not like the convoluted look - I made a separate column for L3.
One question, how do I distinguish f.e. the single 2MB cache from the 2 x 1MB cache types.
I have looked at the raw data and there are still some L3 cache sizes in the L2 column and I can't see any L3 colum, which S-Spec has one?
I would like the L3 column to be just after the L2 column, is this OK with you?
I assume 2MB vs. 2 x 1MB is for Core 2 CPU L2 caches, in general if it's Quad Core it's 2 x nMB and Six core is 3 x nMB
I feel I need a file with the L3 cache sorted out, when might one be possible?
106A4 Bloomfield-2666 SLBCH C0 2008 Core i7 4 x 256K + 8M
106A4 Bloomfield-2933 SLBCK … … …
106A4 Bloomfield-3200 SLBCJ … … …
106A5 Bloomfield-2666 SLBEJ D0 … …
106A5 Bloomfield-2800 SLBKP … … …
106A5 Bloomfield-3066 SLBEN … 2009 …
106A5 Bloomfield-3200 SLBEU … … …
106A5 Bloomfield-3333 SLBEQ … … …
206C2 Gulftown-3200 SLBVF B1 2010 Core i7 970 6 x 256K + 12M
206C2 Gulftown-3333 SLBUZ … … Core i7 980X 6 x 256K + 12M
206C2 … SLBYU … 2011 Core i7 980 6 x 256K + 12M
206C2 Gulftown-3466 SLBVZ … … Core i7 990X 6 x 256K + 12M
206D6 Sandy Bridge-E-3600 QBM0 C1 … Core i7 4 x 256K + 10M
206D7 … SR0LD C2 2012 …
206D6 Sandy Bridge-E-3200 SR0H9 C1 2011 Core i7 6 x 256K + 12M
206D6 Sandy Bridge-E-3300 SR0GW … … Core i7 6 x 256K + 15M
206D7 Sandy Bridge-E-3200 SR0KY C2 … Core i7 6 x 256K + 12M
206D7 Sandy Bridge-E-3300 SR0KF … … Core i7 6 x 256K + 15M
206D7 Sandy Bridge-E-3500 SR0WR … 2012 …
306E4 Ivy Bridge-E-3700 SR1AU S1 2013 Core i7 4 x 256K + 10M
306E4 Ivy Bridge-E-3400 SR1AT … … Core i7 6 x 256K + 12M
306E4 Ivy Bridge-E-3600 SR1AS … … Core i7 6 x 256K + 15M
306F2 Haswell-E-3300 SR20S R2 2014 …
306F2 Haswell-E-3500 SR20R … … …
306F2 Haswell-E-3000 SR20Q … … Core i7 8 x 256K + 20M
406F1 Broadwell-E-3400 SR2PD R0 2016 Core i7 6 x 256K + 15M
406F1 Broadwell-E-3600 SR2PC … … …
406F1 Broadwell-E-3200 SR2PB … … Core i7 8 x 256K + 20M
406F1 Broadwell-E-3000 SR2PA … … Core i7 10 x 256K + 25M
50654 Skylake-X-3500 SR3L4 U0 2017 Core i7 7800X 6 x 1M + 8.25M
50654 Skylake-X-3600 SR3L5 … … Core i7 7820X 8 x 1M + 11M
50654 Skylake-X-3300 SR3L2 … … Core i9 7900X 10 x 1M + 13.75M
50654 Skylake-X-2900 SR3NG … … Core i9 7920X 12 x 1M + 15.5M
50654 Skylake-X-3100 SR3RQ … … Core i9 7940X 14 x 1M + 19.25M
50654 Skylake-X-2800 SR3RR … … Core i9 7960X 16 x 1M + 22M
50654 Skylake-X-2600 SR3RS … … Core i9 7980XE 18 x 1M + 24.75M
50654 Skylake-X-3800 SR3NH M0 2018 Core i7 9800X 8 x 1M + 16.5M
50654 Skylake-X-3300 SREZ8 … … Core i9 9820X 10 x 1M + 16.5M
50654 Skylake-X-3500 SREZ7 … … Core i9 9900X 10 x 1M + 19.25M
50654 … SREZ6 … … Core i9 9920X 12 x 1M + 19.25M
50654 Skylake-X-3300 SREZ5 … … Core i9 9940X 14 x 1M + 19.25M
50654 Skylake-X-4000 SREZA … … Core i9 9940XE 14 x 1M + 19.25M
50654 Skylake-X-3100 SREZ4 … … Core i9 9960X 16 x 1M + 22M
50654 Skylake-X-3000 SREZ3 … … Core i9 9980XE 18 x 1M + 24.75M
50657 Cascade Lake-X-3700 SRGV7 L1 2019 Core i9 10900X 10 x 1M + 19.25M
50657 Cascade Lake-X-3500 SRGSJ … … Core i9 10920X 12 x 1M + 19.25M
50657 Cascade Lake-X-3300 SRGSH … … Core i9 10940X 14 x 1M + 19.25M
50657 Cascade Lake-X-3000 SRGSG … … Core i9 10980XE 18 x 1M + 24.75M
It could have been yesterday but I got cut off from/by the Vogons server.
PARKE wrote on 2025-06-18, 08:02:I got cut off from/by the Vogons server.
Thank you and OK, I also noted of late it has had issues, but as yet have not found a post about what they are.
SIV said "Checked 2243 entries from D:\SIV\SSpec.tsv in 0.053 seconds, found 264 issues, 1679 undated, 54 with no cache size, 13 duplicate s-spec, 2 + 283 missing and skipped 89 + 352"
The 2 missing are SL4G7(2) + SLBQK and I suspect SL4G7(2) needs double adding and that SLBQK does not exist.
SLBN3 B1 0106E5h 1,87GHz Xeon 3000 45-nm Lynnfield LV 4 x 256KB 8MB LGA 1156 may 2010 45 065-1.40 1333 1866.00 14 BV80605004737AA Intel Spec Update 32237301.pdf 1333MHz
I expect the , should be a .
More once I have tweaked the SIV parsing.
https://en.wikipedia.org/wiki/List_of_I ... 22_(45_nm) says SLBPT is 2010.
There are 62 L2 missing from two update sheets; they are near the bottom of the SIV18-6 list. The last Intel sheets only list L3 and I can't find relevant/thrustworthy info on these L2's.
Entries from individual Intel sheets are kept together and newer findings are added to their ' family' but I can't position SLAVG & SLBP3 - help !