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x86 APIC and focus processors?

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First post, by superfury

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According to the documentation I can find, they al say that the focus processor (if there is one) is the processor that has a pending request or is servicing it.

What is the purpose of this? If it has a pending request (the IRR bit is set), it can't handle said interrupt?
And if it's servicing it, it may be able to handle it later, assuming the IRR bit isn't set?

Or is the interrupt simply delayed from being received, causing retries on the bus until it can actually receive it?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 2, by superfury

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Also, from what I can see, NT 4.0 configures all CPUs to be have focus (the bit is cleared). So why would it do that? Or is the default value (zero) incorrect?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 2 of 2, by superfury

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Something slightly related: the manuals mention some Arb ID register being used when receiving a INIT deassert IPI. Is it just the Arbitration Priority register being set in some unknown way, or is it something else (some unknown or undocumented register)? It mentions loading some Arbitration ID register from the APIC ID register, but there exists no "Arbitration ID" register according to the listings of the Local APIC?
Edit: Apparently the "Arbitration ID" (Arb ID) register is the Arbitration Priority Register(APR)?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

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