GigAHerZ wrote on Today, 13:16:

Oh boy, oh boy, oh boy! MR BIOS for SIS471 has arrived!

I wonder if it configures the chipset to use 7+1 dirty/tag bits instead of 8+0. The cache would never do write-back properly if it doesn't have that set. (I've made award bios modifications to fix that)
Theoretically, if there exists a SIS471 board with 10 cache chips (8 for data, 1 for tag, 1 for dirty) then 8+0 would work. But i don't think this kind of SIS471 board was ever produced...

Looking at the registers I see this:

register 72 is set to 3, which is:
bit 7: Clock throthling disabled
bit 6: CPUCLK scaling disabled
bit 5-3: CPUCLK scaling control SMOUT0
bit 2-1: (0 1)
pin 116 = RAS4*
pin 133 = ALT
pin 134 = ALTWL*
pin 137 = RAS5*

register 50: I see A8 so 1010 1000
bit 7-6: DRAM speed faster
bit 5: 1T Write CAS
bit 4: Internal CPU cache write back disabled (should only be 1 on P24T/D or M6/M7)
bit 3: External cache write back enabled
bit 2-0: off and not relevant for 486.

register 51 I see DE so 1101 1110
bit 7: cache enabled
bit 6-4: cache size 1MB
bit 3: cache interleave enabled
bit 2: cache on
bit 1 and 0: lowest cache burst latency

Here is what speedsys shows.

I don't see any option in the BIOS for changing between write back and write through. I do wonder if the fact I have 128Kx8 cache chips including for the tag ram means it is using the unused half of the tag ram for the dirty bits. It only needs a 64Kx8 SRAM for tag on 1MB cache, and it needs 64Kx1 for alter ram and the data sheet does mention something about sharing an SRAM for both. Perhaps if I had the smaller tag ram it would have to switch to the 7+1 tag+alter setup.

lsorense wrote on Yesterday, 20:06:

Hmm, for some reason I didn't think that was allowed, but it does appear many people have done so. […]
Show full quote

weedeewee wrote on Yesterday, 19:59:

Can't you just attach the file to a comment you're making here? Just like in all the other bios threads were the bios files are attached to the comments people post.

another option would be to go to theretroweb discord and do an improve board request to add the biosfile to the specific board page.

Hmm, for some reason I didn't think that was allowed, but it does appear many people have done so.

Well here it is. Maybe someone can give it a try.

The attachment MRBIOS-SIS471-V3-21.zip is no longer available

HOLY! WHAT!? FOR REAL!?!?!

I will try this VERY soon.

Or perhaps the flat blue line means write back caching is in fact not working?

appiah4 wrote on Today, 15:10:

HOLY! WHAT!? FOR REAL!?!?!

I will try this VERY soon.

Well I hope someone tells me if I managed to dump it correctly. If not, the programmer to attempt to read the chip will be here soon.

I have been using that BIOS on this board for 30 years. I didn't realize it was "lost".

lsorense wrote on Today, 15:17:

Well I hope someone tells me if I managed to dump it correctly. If not, the programmer to attempt to read the chip will be here soon.

It works on 86box, so dump has no problem with cheksum

First of all, a big THANK YOU to Isorense for sharing this MR BIOS for SiS471, I thought it was lost forever after that Gigabyte motherboard was bought and nothing came out of it.

Now, I have tested the BIOS on an Acer/AOpen VI15G, a SiS471-based motherboard I have at hand and I'm pleased to report that it works, so the dump is correct! Again, thanks a lot!

I still need to do some more tests (I will try to continue today after work), but as far as I can tell this BIOS does not use the dirty tag bit for L2 WB cache (CTCM also displays 'Dirty Tag: n/a'), so memory performance is less than ideal and much like Isorense I cannot find an option to set L2 to WT. I still have to test CTCHIP34 to see what the BIOS is setting on the different chipset registers...

Note that this is with 256KB of L2, this board also supports 512KB so I may try that option if I can find some chips. One thing I noticed is that my memory bandwidth in Speedsys is much slower than the one posted by Isorense (around 34MB/s vs > 180MB/s) so I may have missed something.

I also had some issues with Turbo switching and RAM waitstates, but I need to dig deeper as I only did some basic tests last night.

I'll update once I have more info!

I tried toggling the register to enable the 7+1 mode, and it appears to have made no difference in performance. write speed is still a constant line in speedsys. Disabling the cache made the speed terrible of course. I didn't see any other registers that seemed related to the L2 cache that should affect the write back cache working.

lsorense wrote on Today, 15:08:

Looking at the registers I see this: […]
Show full quote

GigAHerZ wrote on Today, 13:16:

Oh boy, oh boy, oh boy! MR BIOS for SIS471 has arrived!

I wonder if it configures the chipset to use 7+1 dirty/tag bits instead of 8+0. The cache would never do write-back properly if it doesn't have that set. (I've made award bios modifications to fix that)
Theoretically, if there exists a SIS471 board with 10 cache chips (8 for data, 1 for tag, 1 for dirty) then 8+0 would work. But i don't think this kind of SIS471 board was ever produced...

Looking at the registers I see this:

register 72 is set to 3, which is:
bit 7: Clock throthling disabled
bit 6: CPUCLK scaling disabled
bit 5-3: CPUCLK scaling control SMOUT0
bit 2-1: (0 1)
pin 116 = RAS4*
pin 133 = ALT
pin 134 = ALTWL*
pin 137 = RAS5*

register 50: I see A8 so 1010 1000
bit 7-6: DRAM speed faster
bit 5: 1T Write CAS
bit 4: Internal CPU cache write back disabled (should only be 1 on P24T/D or M6/M7)
bit 3: External cache write back enabled
bit 2-0: off and not relevant for 486.

register 51 I see DE so 1101 1110
bit 7: cache enabled
bit 6-4: cache size 1MB
bit 3: cache interleave enabled
bit 2: cache on
bit 1 and 0: lowest cache burst latency

Here is what speedsys shows.

The attachment 20260210_095322-small.jpg is no longer available

I don't see any option in the BIOS for changing between write back and write through. I do wonder if the fact I have 128Kx8 cache chips including for the tag ram means it is using the unused half of the tag ram for the dirty bits. It only needs a 64Kx8 SRAM for tag on 1MB cache, and it needs 64Kx1 for alter ram and the data sheet does mention something about sharing an SRAM for both. Perhaps if I had the smaller tag ram it would have to switch to the 7+1 tag+alter setup.

Very good results as for DX2/66! Congradulations!

Here my results on FIC 486-VIO-IO with Intel DX2/66 fine tuned write-back system.

Your write also just shows a flat line at 40MB/s. How do you determine that write back caching is in fact working? I would have expected small writes under the L2 cache size should be much faster but maybe I am not understanding how the test is supposed to work.

ctcm doesn't work, since it appears it doesn't handle my 1MB L2 cache and can't determine the L2 cache size and type.