No the problem occurs even at base clock 2Ghz for ML-37. Difference in behaviour at 2.0, 2.2, 2.4Ghz is just a timing issue being exposed. You need very rigorous testing at multiple CPU frequencies to confirm CR1 is stable.

Right now I'm trying 1x Kingston HyperX 1GB and 1x OCZ Platinum 1GB DDR400 together. CR1 may work with 2x Corsair or 2x OCZ Platinum, but I don't have those.

The IMC is very timings dependent, even stock timings might not be a good choice for a particular core revision and CR1 is even more difficult, sometimes a little ram overvolt might help a lot .

Mixing different brands with the same memory ICs may work, while same brand with different memoy ICs may not work stable at all.

In the mid-2000s, it was common knowledge that socket 754 processors needed to be overclocked with a single memory module to reduce the load on the memory controller.
The quality of the memory itself isn't the issue; the weak point in this case is the processors themselves. AMD positioned this platform as a budget platform, planning for socket 939, which was released much later, making socket 754 the default platform for the time, while remaining budget-oriented by design.

Kruton 9000 wrote on Yesterday, 16:17:

In the mid-2000s, it was common knowledge that socket 754 processors needed to be overclocked with a single memory module to reduce the load on the memory controller.
The quality of the memory itself isn't the issue; the weak point in this case is the processors themselves. AMD positioned this platform as a budget platform, planning for socket 939, which was released much later, making socket 754 the default platform for the time, while remaining budget-oriented by design.

This is not about standard 754 CPUs, these are mobiles, latest 754 core (basically single channel 939 with low leakage transistors and memory controller new stepping) IMC is revised and better than the 130 cpus one; the signal integrity is also influenced by motherboards traces/shielding and planes layout, given the same specs (chipset, VRMs, etc etc) there are better boards with less noise and there are some that are just terrible (when you push them out of the stock frequency comfort zone); but as you said less memory modules are better for signal integrity, it was also true that to maintain stability with something like winbond bh5 memory at very high clocks it was common to modify the motherboard ram vrm to provide up to 3.0/3.2V to memory slots, which was a massive overvolt from 2.6V, but bh5 loved it.
Addressing these caveats was the reason why DFI LanParty boards (6 layers, better traceroute, better shielding, huge ram overvolting capabilities) were so praised by the OC community.

Madowax wrote on Today, 04:04:

Kruton 9000 wrote on Yesterday, 16:17:

In the mid-2000s, it was common knowledge that socket 754 processors needed to be overclocked with a single memory module to reduce the load on the memory controller.
The quality of the memory itself isn't the issue; the weak point in this case is the processors themselves. AMD positioned this platform as a budget platform, planning for socket 939, which was released much later, making socket 754 the default platform for the time, while remaining budget-oriented by design.

This is not about standard 754 CPUs, these are mobiles, latest 754 core (basically single channel 939 with low leakage transistors and memory controller new stepping) IMC is revised and better than the 130 cpus one; the signal integrity is also influenced by motherboards traces/shielding and planes layout, given the same specs (chipset, VRMs, etc etc) there are better boards with less noise and there are some that are just terrible (when you push them out of the stock frequency comfort zone); but as you said less memory modules are better for signal integrity, it was also true that to maintain stability with something like winbond bh5 memory at very high clocks it was common to modify the motherboard ram vrm to provide up to 3.0/3.2V to memory slots, which was a massive overvolt from 2.6V, but bh5 loved it.
Addressing these caveats was the reason why DFI LanParty boards (6 layers, better traceroute, better shielding, huge ram overvolting capabilities) were so praised by the OC community.

Re: Battle of the platforms: socket 754!
To be honest, there isn’t much difference between the Venice core and the Lancaster.
It boils down to a difference of 512 KB versus 1 MB of L2 cache.

Venice wasn't even tested thoroughly in this thread, neither was Lancaster with L2 512kB. One LinX benchmark is insufficient. You are welcome to run test suite of nd22. Skip tests that are not essential. For CPU we have PCMark 2002, 2004, 2005, SuperPI and Cinebench 2003.

We have Clawhammer vs Newcastle (different L2 size) and Clawhammer vs Lancaster (same L2 size).

shevalier wrote on Today, 07:27:

Re: Battle of the platforms: socket 754! To be honest, there isn’t much difference between the Venice core and the Lancaster. It […]
Show full quote

Madowax wrote on Today, 04:04:

Kruton 9000 wrote on Yesterday, 16:17:

In the mid-2000s, it was common knowledge that socket 754 processors needed to be overclocked with a single memory module to reduce the load on the memory controller.
The quality of the memory itself isn't the issue; the weak point in this case is the processors themselves. AMD positioned this platform as a budget platform, planning for socket 939, which was released much later, making socket 754 the default platform for the time, while remaining budget-oriented by design.

This is not about standard 754 CPUs, these are mobiles, latest 754 core (basically single channel 939 with low leakage transistors and memory controller new stepping) IMC is revised and better than the 130 cpus one; the signal integrity is also influenced by motherboards traces/shielding and planes layout, given the same specs (chipset, VRMs, etc etc) there are better boards with less noise and there are some that are just terrible (when you push them out of the stock frequency comfort zone); but as you said less memory modules are better for signal integrity, it was also true that to maintain stability with something like winbond bh5 memory at very high clocks it was common to modify the motherboard ram vrm to provide up to 3.0/3.2V to memory slots, which was a massive overvolt from 2.6V, but bh5 loved it.
Addressing these caveats was the reason why DFI LanParty boards (6 layers, better traceroute, better shielding, huge ram overvolting capabilities) were so praised by the OC community.

Re: Battle of the platforms: socket 754!
To be honest, there isn’t much difference between the Venice core and the Lancaster.
It boils down to a difference of 512 KB versus 1 MB of L2 cache.

There is a huge difference between Clawhammer/Newcastle and Venice/Lancaster/Newark though, especially the IMC, it is on par of the SanDiego core updates and the mobiles retain the full 1MB cache, they are basically 754 Single Channel SanDiego cores 😉