Hi Jan,

I have tried adding an ISA slot to a GA-7ZXE rev 2.1 board which has footprint for one, but I have run into problems and I'm wondering if BIOS lacks some functionality that is needed for ISA. So far I have enabled some DMA configs for the BIOS with AMIBCP and added a missing passive component to board (DACK5 was not connected to pin on ISA slot at all, adding a resistor or piece of wire was needed). Now AWE64 gets correctly assigned to IRQ 5 and DMAs 1 and 5. However it's still not functional, Creative's diagnose.exe correctly recognizes the IRQ and DMA settings and is able to play some garbled audio, but CTCM complains about incorrect Vendor ID and Windows gives Code 9 error.

I have been using version FB BIOS downloaded from Gigabyte's site, it and the version modded with AMIBCP are in the attached zip file.

Can you test 8 bit sound/mode/drivers on that card?
I have a hunch that there's a another dead trace in the 16bit area.

myne wrote on 2026-05-28, 11:20:

Can you test 8 bit sound/mode/drivers on that card?
I have a hunch that there's a another dead trace in the 16bit area.

That's where my mind goes to, a bridged or dead line causing data corruption

I have already traced most of the traces in 16 bit area to test points near south bridge, and they seem to be fine. I suppose other DACK/DRQ lines than 5 and IRQs don't matter as they aren't used anyways?

Diagnose.exe's 8bit test was also a bit garbled, but in a regular and not random way. Same as 16bit test actually. However, I tried TIE fighter's install program and I could set it as a Sound Blaster 2.0 and the digital sound test would sound okay-ish. Music test didn't work, not even FM one.

Wait.
Don't you need an xtal too?
Pretty sure they needed a boost over the pci clock.

myne wrote on Yesterday, 16:10:

Wait.
Don't you need an xtal too?
Pretty sure they needed a boost over the pci clock.

I think I actually measured ISA clock from the bus and it looked fine. But apparently AWE64 doesn't use it, as there's no contact on that pin.

It probably is divided by four from PCI clock and comes from south bridge. What do you mean with a boost?

I just meant I thought the Southbridge needed its own isa xtal because the pci one was too weak to drive both.

You're on a via chipset. Yes?
Those can run different isa clocks. You might want to find the datasheet, and wpcredit or similar.

About a year or so ago I read a bunch of the datasheets from that era so I shouldn't be too confused.

It's possible the board conversation tools in my sig could help. I doubt there's much difference between an Asus and gigabyte on a via chipset on the isa side.
I can send a few hundred converted Asus boards if there is somewhere to upload. (~200mb)

myne wrote on Today, 00:29:

I just meant I thought the Southbridge needed its own isa xtal because the pci one was too weak to drive both. […]
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I just meant I thought the Southbridge needed its own isa xtal because the pci one was too weak to drive both.

You're on a via chipset. Yes?
Those can run different isa clocks. You might want to find the datasheet, and wpcredit or similar.

About a year or so ago I read a bunch of the datasheets from that era so I shouldn't be too confused.

It's possible the board conversation tools in my sig could help. I doubt there's much difference between an Asus and gigabyte on a via chipset on the isa side.
I can send a few hundred converted Asus boards if there is somewhere to upload. (~200mb)

A crystal doesn't drive clock directly, but there are various circuits such as probably a PLL and an output buffer before it actually gets to the bus.

It is KT133A chipset, so south bridge is 686B. From the datasheet you posted, it looks like ISA clock really is just generated from PCI clock with a divider, after which there's probably another buffer.

Do you have something like a PicoGUS where you can do data reads over the ISA bus with an expected value?

The nature of the corruption may reveal itself

NeoG_ wrote on Today, 11:12:

Do you have something like a PicoGUS where you can do data reads over the ISA bus with an expected value?

The nature of the corruption may reveal itself

Unfortunately I don't. 🙁 I was thinking the same that some sort card that can be used for debugging ISA might be needed to solve this. Although PicoGUS seems to be 8bit so it won't help if the problem is in the 16bit section.

I did buy a POST diagnostics card from Aliexpress, and it'll probably arrive next week. Maybe that'll help with checking whether basic ISA functionality exists?

Mike_ wrote on Today, 10:23:

A crystal doesn't drive clock directly, but there are various circuits such as probably a PLL and an output buffer before it act […]
Show full quote

myne wrote on Today, 00:29:

I just meant I thought the Southbridge needed its own isa xtal because the pci one was too weak to drive both. […]
Show full quote

I just meant I thought the Southbridge needed its own isa xtal because the pci one was too weak to drive both.

You're on a via chipset. Yes?
Those can run different isa clocks. You might want to find the datasheet, and wpcredit or similar.

About a year or so ago I read a bunch of the datasheets from that era so I shouldn't be too confused.

It's possible the board conversation tools in my sig could help. I doubt there's much difference between an Asus and gigabyte on a via chipset on the isa side.
I can send a few hundred converted Asus boards if there is somewhere to upload. (~200mb)

A crystal doesn't drive clock directly, but there are various circuits such as probably a PLL and an output buffer before it actually gets to the bus.

It is KT133A chipset, so south bridge is 686B. From the datasheet you posted, it looks like ISA clock really is just generated from PCI clock with a divider, after which there's probably another buffer.

The attachment isa_clock.png is no longer available

Yeah, but the pci clock comes from the same clockgen chip that does the cpu and ram. I seem to recall SBs needing a secondary crystal even if the result lines up with pci/x.
In any case, the board I saw a pic of without isa had one next to the chipset so I assume ops does too.

Op take a look in my sig for the bx reference design.
Might give some ideas.