Looks like it mostly throttles IO or maybe bus.

Here is the code. Its not a final version still working on it. Works thrue chipset PCI registers.

may be it need a bit of explanation. I have a retro DOS machine based on that celeron 400, and some games is hate this high speeds, slower machine I don't have, instead I can write some useful code. That's what that.

I made it even more slower, so I can say it is success. I have it compiled with MS C++ 7.0 under MSDOS 6.22. I rewrote source a bit modify and reduce some garbage. Still have to reduce the size of tool. I use 3 standart libs, and the size is huge) hope make some time and rewrite stuff simplier. Later. If some one have a wish to test or use, please write to me.

Looked at the code. So you are using ACPI Processor Control Register (P_CNT) to throttle CPU. While I cant find real full VT82C596A datasheet, there is one for vt82c686b https://theretroweb.com/chip/documentation/vt … b8269986481.pdf :

>During normal operation, two mechanisms are provided to modulate CPU execution and control power consumption by
throttling the duty cycle of STPCLK#:

1. Setting the THT_EN bit to 1, the duty cycle defined in THT_DTY (IO space Rx10) is used.
2. THRM# pin assertion enables automatic clock throttling with duty cycle pre-configured in THM_DTY (PCI configuration Rx4C).

So this is exactly how https://github.com/scrapcomputing/ThrottleBlaster works, but in software! Nice 😀

Your tool sets both Rx10 and Rx4C. According to datasheet you can skip Rx4C as its only active when thermal throttling requested by physical signal send by CPU via THRM# pin. You are writing SPEED_SLOW 0x12 aka 0001 0010

>4 Throttling Enable (THT_EN)
Setting this bit starts clock throttling (modulating the STPCLK# signal) regardless of the CPU state.
The throttling duty cycle is determined by bits 3-0 of this register.
3-0 Throttling Duty Cycle (THT_DTY)
This 4-bit field determines the duty cycle of the STPCLK# signal when the system is in throttling
mode (the "Throttling Enable" bit is set to one). The duty cycle indicates the percentage of time the
STPCLK# signal is asserted while the Throttling Enable bit is set. The field is decoded as follows:

0000 Reserved
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%

I wonder if vt82c686b extended to 4 bits or if VT82C596A already supported it, have you tried 0x11? 😀

Looking at other period chipsets this ACPI interface is universal so there is no need for checking for VIA soughbridge. For example Intel PIIX4 https://theretroweb.com/chip/documentation/29 … b4631654578.pdf supports same thing:

7.2.7. PCNTRL—PROCESSOR CONTROL REGISTER (IO)
I/O Address: Base + (10h)
4 Throttle Enable (THT_EN)—R/W. 1=Enable system throttle clock control. 0=Disable.
3:1 Throttle Duty Programming Bits (THTL_DTY)—R/W. Selects the duty cycle of the STPCLK#
signal when the system is in the system throttling mode. The duty cycle indicates the percentage of
time the STPCLK# signal is asserted while in the throttle mode. The field is decoded as follows:
Bits[2:0] Mode Bits[2:0] Mode
000 Reserved 100 50%
001 12.5% 101 62.5%
010 25% 110 75%
011 37.5% 111 87.5%

Even older Intel 82371FB (PIIX) AND 82371SB (PIIX3) did support something similar https://theretroweb.com/chip/documentation/82 … c0627455529.pdf with much higher granularity:
CTLTMR—CLOCK SCALE STPCLK# LOW TIMER (Function 0)
Address Offset: ACh
The value in this register defines the duration of the STPCLK# asserted period when bit 2 in the SMICNTL
Register is set to 1. The value in this register is loaded into the STPCLK# Timer when STPCLK# is asserted.
The STPCLK# timer is a divide by PCI clock. The base count for a value of 0 is 42 µsec for a 50 MHz time
base, 35 µsec for a 60 MHz time base, 32 µsec for a 66 MHz time base. These numbers are determined as
follows: # of PCI clocks STPCLK# is asserted (or negated) = 1 + 1056 X (programmed value in register +1).

2.2.24. CTHTMR—CLOCK SCALE STPCLK# HIGH TIMER (Function 0)
Address Offset: AEh
The value in this register defines the duration of the STPCLK# negated period when bit 2 in the SMICNTL
Register is set to 1. The value in this register is loaded into the STPCLK# Timer when STPCLK# is negated.
The STPCLK# timer is a divide by PCI clock. The base count for a value of 0 is 42 µsec for a 50 MHz time
base, 35 µsec for a 60 MHz time base, 32 µsec for a 66 MHz time base. These numbers are determined as
follows: # of PCI clocks STPCLK# is asserted (or negated) = 1 + 1056 X (programmed value in register +1).

Pretty neat.

>Still have to reduce the size of tool.

why? is it really that big? I would add taking a parameter so you can control the slowdown %.

Yes every thing is correct. I have used datasheet for Vt82C596B and it worked. yes, I have excluded Rx4C, wrong way. 0x11 also tryed max slow state, like described in datasheet. my calculations show 6,21%. Also I will add the command line args, to make life easy and already it takes parameter in new version. About size, something around 9 KB). here is not latest but reworked source.