Mov Ew,Sw Question \ VOGONS

Mov Ew,Sw Question

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First post, by danoon

Posted on 2011-04-11, 17:41

danoon Offline

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Normal core

1CASE_D(0x8c)												/* Mov Ew,Sw */
2			{
3				GetRM;Bit16u val;Bitu which=(rm>>3)&7;
4				switch (which) {
5				case 0x00:					/* MOV Ew,ES */
6					val=SegValue(es);break;
7				case 0x01:					/* MOV Ew,CS */
8					val=SegValue(cs);break;
9				case 0x02:					/* MOV Ew,SS */
10					val=SegValue(ss);break;
11				case 0x03:					/* MOV Ew,DS */
12					val=SegValue(ds);break;
13				case 0x04:					/* MOV Ew,FS */
14					val=SegValue(fs);break;
15				case 0x05:					/* MOV Ew,GS */
16					val=SegValue(gs);break;
17				default:
18					LOG(LOG_CPU,LOG_ERROR)("CPU:8c:Illegal RM Byte");
19					goto illegal_opcode;
20				}
21				if (rm >= 0xc0 ) {GetEArd;*eard=val;}
22				else {GetEAa;SaveMw(eaa,val);}
23				break;
24			}

Should that GetEard be GetEarw?

Reply 1 of 6, by wd

Posted on 2011-04-11, 17:50

wd Offline

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Yes, looks like it should read

1{GetEArw;*earw=val;}

for the non-prefixed and 0x66 prefixed variant.

Reply 2 of 6, by danoon

Posted on 2011-04-11, 18:04

danoon Offline

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Maybe a solution could be to remove CASE_D(0x8c) and replace CASE_W(0x8c) with CASE_B(0x8c)?

Reply 3 of 6, by wd

Posted on 2011-04-11, 18:53

wd Offline

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I've checked sandpile and AMD docs, both define the instruction as register-dword but
memory-word only function (the first using zero-extension of the seg reg) so the current
implementation in dosbox matches this (if i'm not completely misreading the bochs sources
this is what they're doing as well).

Reply 4 of 6, by danoon

Posted on 2011-04-11, 19:05

danoon Offline

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Thanks for checking that. I'll add a comment to the java cores that it is intentional so that I don't trip myself up again. 😀

https://github.com/danoon2/Boxedwine

Reply 5 of 6, by wd

Posted on 2011-04-11, 19:13

wd Offline

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Well i can't claim the code is correct, but all hints at that even though it kicks orthogonality quite hard.

Reply 6 of 6, by peterferrie

Posted on 2011-04-16, 15:30

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It is correct. The register is zero-extended in 32-bit mode, even though a selector is only 16 bits.

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