386s and 486s both require *four* 30 pin SIMMs for operation. 4x8-bit=32 bit. All 386DX and 486 systems read memory in 32-bit chunks. The first 386 came out in 1985 or 1986.

Performance of 30-pin and 72-pin SIMMs is more or less the same provided they are using similar IC types. 72-pin SIMMs may allow slightly faster memory timings due to having less electrical contacts though.

So an 386 system system using 4 sticks at once? But if one stick of 72pin simm memory is 32-bit how does it work in a system with 72pin memory? Would the system using one 72-pin stick at once?

(sorry for my low-quality english, sometimes i do better, and often its just a word puzzle. ( i actually trying to do my best.. But if i have busy days from my work, my brain wont corperate)

Robin4 wrote:

So an 386 system system using 4 sticks at once? But if one stick of 72pin simm memory is 32-bit how does it work in a system with 72pin memory? Would the system using one 72-pin stick at once?

(sorry for my low-quality english, sometimes i do better, and often its just a word puzzle. ( i actually trying to do my best.. But if i have busy days from my work, my brain wont corperate)

When using multiple 72pin SIMM's, you're not changing the width of the addressable memory. It's still 32bits. The difference is your adding address space to the top end of the addressable memory. So the BIOS just reports a higher max memory address. Essentially you're adding to the "length" of memory, not the "width".

386DXs and 486s (all) have a 32-bit data bus, so they require groups of four 30 pin SIMMs (you can't, for example, use 6, it's either 4 or 😎 or any number of 72 pin SIMMs (one used at a time). When using 30 pin SIMMs they are used in parallel, so each read/write operation will read simultaneously one byte from each stick. There is no speed penalty, because you are still fetching 32 bits per operation.

286s and 386SXs have a 16-bit data bus, so they require groups of two 30 pin SIMMs (2, 4, 6 ...).

Robin4 wrote:

- If an 30 pin simm could transfer 8-bits of data at a time, how is this data stored in these memory chips? Would it be that every bit is stored in on memory chip? (if the simm has 9 chips in the stick)

Exactly. If an 8-bit wide module has 8(9) chips on it then each chip stores 1 bit for each memory cell (plus the extra parity bit if present). Power, address and strobe lines are connected in parallel between all chips and their data pins go individually to each line in the data bus. If such an 8-bit module has 2(3) chips on it then each one is 4 bits wide, a 32-bit module with 4 chips means they're 8-bit wide each and so on. Larger modules (SDRAM and beyond) might be laid out differently (i.e 128Mx4 instead of 64Mx8) which can cause some systems to recognize only half or less of the module's capacity because even though it's the same total number of cells, they're organized in a different two-dimensional array and some chipsets can't cope with that.

Don't forget Pentium - using a 64 bit data bus (though it's only a 32 bit CPU), it needed 72 pin SIMMs in pairs (other than the odd few boards which had a slow single SIMM mode that buffered two accesses).

Harking back to the 386 & 30 pin SIMM era, there were also examples using 8 SIMMs as two interleaved banks. By alternating the access and prepare parts of the cycle, data could be transferred twice as fast - a popular arrangement for a 386DX20

Anonymous Coward wrote:

386s and 486s both require *four* 30 pin SIMMs for operation. 4x8-bit=32 bit. All 386DX and 486 systems read memory in 32-bit chunks. The first 386 came out in 1985 or 1986.

I wouldn't say all. The CPU has a 32-bit bus, but the chipset can connect to the memory with a wider bus. I have an NCR 3314 (like this one) with an ALR Powercache 4 chipset which has a 64-bit memory bus and requires 8 30-pin SIMMs per bank. I will have to do some benchmark one day to see if it really has any benefits.

GL1zdA wrote:

Anonymous Coward wrote:

386s and 486s both require *four* 30 pin SIMMs for operation. 4x8-bit=32 bit. All 386DX and 486 systems read memory in 32-bit chunks. The first 386 came out in 1985 or 1986.

I wouldn't say all. The CPU has a 32-bit bus, but the chipset can connect to the memory with a wider bus. I have an NCR 3314 (like this one) with an ALR Powercache 4 chipset which has a 64-bit memory bus and requires 8 30-pin SIMMs per bank. I will have to do some benchmark one day to see if it really has any benefits.

Bit of a cliff-hanger... how did this thread drop off in 2015 with no reply!?

What is this Powercache 4 chipset? Did you get around to testing the system?

Were there any benefits to having 64-bit addressing with a 32-bit CPU?

A thread would be great! 😁

I've tested it with Speedsys, but don't remember the results. What I do remember is I couldn't get Speedsys to write the PCX/TXT files with results (it would always hang, even when launched in automated mode), so I have to repeat the tests and take a photo with a camera. Let me know if you want me to do some additional tests. I wouldn't be surprised, if the only benefit of 64-bit memory would be better performance when doing heavy I/O additionaly to heavy CPU use.

Were there any benefits to having 64-bit addressing with a 32-bit CPU?

A thread would be great! 😁

It wouldn't be 64-bit addressing, but rather a 64-bit data path. I also don't see how that interfaces to a 486 CPU. Maybe it's just 64-bit between the cache and the DRAM.
There are 486 systems that have 32-bit memory interleaving that require 8 SIMMs, but normally you can disable that feature and just use 4.

Anonymous Coward wrote:

Were there any benefits to having 64-bit addressing with a 32-bit CPU?

A thread would be great! 😁

It wouldn't be 64-bit addressing, but rather a 64-bit data path. I also don't see how that interfaces to a 486 CPU. Maybe it's just 64-bit between the cache and the DRAM.
There are 486 systems that have 32-bit memory interleaving that require 8 SIMMs, but normally you can disable that feature and just use 4.

I'm guessing it would have somehow processed the first 32-bit, then afterwards process the second 32-bit lot using some intermediary i.e. chipset that supports 64-bit addressing that can also communicate with a 32-bit CPU. Just a thought as I don't really know well this era of hardware.

What 486 systems memory interleave? I know there are some 386 systems (SIS Rabbit) do they need 8 SIMM's too?

GL1zdA wrote:

I've tested it with Speedsys, but don't remember the results. What I do remember is I couldn't get Speedsys to write the PCX/TXT files with results (it would always hang, even when launched in automated mode), so I have to repeat the tests and take a photo with a camera. Let me know if you want me to do some additional tests. I wouldn't be surprised, if the only benefit of 64-bit memory would be better performance when doing heavy I/O additionaly to heavy CPU use.

No that's ok... I only got curious after making the ALR connection... learning that one of their earlier chipset's went onto double the I/O bandwidth.

ALR systems are cool.