1OPTINLINE void decodeCPUaddress(byte towrite, uint_32 offset, byte *planes, uint_32 *realoffset)
2{
3	if (ActiveVGA->registers->SequencerRegisters.REGISTERS.SEQUENCERMEMORYMODEREGISTER.Chain4Enable) //Chain 4 mode?
4	{
5		*realoffset = offset; //Original offset to start with!
6		offset &= 0x3; //Walk through the planes!
7		*planes = (1 << offset); //Lower bits, create bitmask!
8		*realoffset >>= 2; //Rest of the bits. Multiples of 4 wont get written!
9		return; //Done!
10	}
11	if (ActiveVGA->registers->GraphicsRegisters.REGISTERS.GRAPHICSMODEREGISTER.OddEvenMode) //Odd/Even mode?
12	{
13		//Odd/even mode used (compatiblity case)?
14		//Do the same as VPC!
15		register byte calcplanes;
16		register uint_32 newoffset;
17		newoffset = offset; //Take the default offset!
18		newoffset &= 0xFFFE; //Take the offset within the plane!
19		if (ActiveVGA->registers->GraphicsRegisters.REGISTERS.MISCGRAPHICSREGISTER.EnableOddEvenMode) //Chain using A0 selected? 0=0/2, 1=1/3!
20		{
21			calcplanes = offset;
22			calcplanes &= 1; //Take 1 bit to determine the plane (0/1)!
23		}
24		else //Normal operations?
25		{
26			calcplanes = 0; //The plane calculated is always 0!
27			newoffset |= (offset & 1); //Linear!
28		}
29		calcplanes = (0x5 << calcplanes); //Convert to used plane (0/2 or 1/3)!
30		*planes = calcplanes; //Load the planes to address!
31		*realoffset = newoffset; //Load the offset to address!
32		return; //Done!
33	}
34
35	if (towrite) //Writing access?
36	{
37		*planes = 0xF; //Write to all planes possible, map mask register does the rest!
38	}
39	else
40	{
41		*planes = 1; //Load plane 0!
42		*planes <<= ActiveVGA->registers->GraphicsRegisters.REGISTERS.READMAPSELECTREGISTER.ReadMapSelect; //Take this plane!
43	}
44	*realoffset = offset; //Direct offset into VRAM!
45	//The offset is used directly!
46}

1word addresswrap(word offset)
2{
3	//word address2;
4	//address2 = memoryaddress; //Load the address for calculating!
5	if (ActiveVGA->precalcs.BWDModeShift == 1) //Word mode?
6	{
7		if (ActiveVGA->registers->CRTControllerRegisters.REGISTERS.CRTCMODECONTROLREGISTER.AW) //MA15 has to be on MA0
8		{
9			//address2 >>= 15;
10			offset &= 0x3FFF; //Wrap around 16KB!
11		}
12	}
13	/*else //MA13 has to be on MA0?
14	{
15		address2 >>= 13;
16	}*/
17	//address2 &= 1; //Only load 1 bit!
18	//result &= 0xFFFE; //Clear bit 0!
19	//result |= address2; //Add bit MA15 at position 0!
20	return offset; //Give the result!
21}
22
23/*
24
25The r/w operations from the CPU!
26
27*/
28
29//decodeCPUaddress(Write from CPU=1; Read from CPU=0, offset (from VRAM start address), planes to read/write (4-bit mask), offset to read/write within the plane(s)).
30OPTINLINE void decodeCPUaddress(byte towrite, uint_32 offset, byte *planes, uint_32 *realoffset)
31{
32	if (ActiveVGA->registers->SequencerRegisters.REGISTERS.SEQUENCERMEMORYMODEREGISTER.Chain4Enable) //Chain 4 mode?
33	{
34		*realoffset = offset; //Original offset to start with!
35		offset &= 0x3; //Walk through the planes!
36		*planes = (1 << offset); //Lower bits, create bitmask!
37		*realoffset >>= 2; //Rest of the bits. Multiples of 4 wont get written!
38		*realoffset <<= ActiveVGA->precalcs.BWDModeShift; //Apply memory address size!
39		*realoffset = addresswrap(*realoffset); //
40		return; //Done!
41	}
42	if (ActiveVGA->registers->GraphicsRegisters.REGISTERS.GRAPHICSMODEREGISTER.OddEvenMode) //Odd/Even mode?
43	{
44		//Odd/even mode used (compatiblity case)?
45		//Do the same as VPC!
46		register byte calcplanes;
47		register uint_32 newoffset;
48		newoffset = offset; //Take the default offset!
49		if (ActiveVGA->registers->GraphicsRegisters.REGISTERS.MISCGRAPHICSREGISTER.EnableOddEvenMode) //Chain using A0 selected? 0=0/2, 1=1/3!
50		{
51			calcplanes = offset;
52			calcplanes &= 1; //Take 1 bit to determine the plane (0/1)!
53		}
54		else //Normal operations?
55		{
56			calcplanes = 0; //The plane calculated is always 0!
57			newoffset |= (offset & 1); //Linear!
58		}
59		newoffset &= 0xFFFE; //Take the offset within the plane!
60		newoffset <<= ActiveVGA->precalcs.BWDModeShift; //Apply memory address size!

61		newoffset = addresswrap(newoffset); //Perform address wrap!
62		calcplanes = (0x5 << calcplanes); //Convert to used plane (0/2 or 1/3)!
63		*planes = calcplanes; //Load the planes to address!
64		*realoffset = newoffset; //Load the offset to address!
65		return; //Done!
66	}
67
68	//Planar access?
69	if (towrite) //Writing access?
70	{
71		*planes = 0xF; //Write to all planes possible, map mask register does the rest!
72	}
73	else
74	{
75		*planes = 1; //Load plane 0!
76		*planes <<= ActiveVGA->registers->GraphicsRegisters.REGISTERS.READMAPSELECTREGISTER.ReadMapSelect; //Take this plane!
77	}
78	*realoffset = offset; //Direct offset into VRAM!
79	*realoffset <<= ActiveVGA->precalcs.BWDModeShift; //Apply memory address size!
80	*realoffset = addresswrap(*realoffset);
81	//The offset is used directly!
82}