UniPCemu 8086+ and 80386+ GRP2 opcodes(shift/rotates) flags \ VOGONS

UniPCemu 8086+ and 80386+ GRP2 opcodes(shift/rotates) flags

Topic actions

First post, by superfury

Posted on 2017-05-25, 18:23

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5912
Joined: 2014-03-08, 11:25
Location: Netherlands

I'm trying to get my 8/16/32-bit shift/rotate(GRP2 opcodes) instructions result in fully correct flags, but for some reason, it doesn't check out in the EPC 80186 testsuite(ran on the UniPCemu 80286 emulation).

GRP2 8-bit

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, oldCF, msb;
4	word backup;
5	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
6	s = oper1b;
7	oldCF = FLAG_CF;
8	if (EMULATED_CPU >= CPU_NECV30) cnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
9	switch (thereg) {
10	case 0: //ROL r/m8
11		for (shift = 1; shift <= cnt; shift++) {
12			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
13			s = s << 1;
14			s = s | FLAG_CF;
15		}
16		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 7) & 1));
17		break;
18
19	case 1: //ROR r/m8
20		for (shift = 1; shift <= cnt; shift++) {
21			FLAGW_CF(s & 1);
22			s = (s >> 1) | (FLAG_CF << 7);
23		}
24		if (cnt==1) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1));
25		break;
26
27	case 2: //RCL r/m8
28		for (shift = 1; shift <= cnt; shift++) {
29			oldCF = FLAG_CF;
30			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
31			s = s << 1;
32			s = s | oldCF;
33		}
34		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 7) & 1));
35		break;
36
37	case 3: //RCR r/m8
38		for (shift = 1; shift <= cnt; shift++) {
39			oldCF = FLAG_CF;
40			FLAGW_CF(s & 1);
41			s = (s >> 1) | (oldCF << 7);
42		}
43		if (cnt==1) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1));
44		break;
45
46	case 4: case 6: //SHL r/m8
47		//FLAGW_AF(0);
48		for (shift = 1; shift <= cnt; shift++) {
49			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
50			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
51			s = (s << 1) & 0xFF;
52		}
53		if (cnt==1) FLAGW_OF((FLAG_CF ^ (s >> 7)));
54		flag_szp8((uint8_t)(s&0xFF)); break;
55
56	case 5: //SHR r/m8
57		if (cnt == 1) FLAGW_OF((s & 0x80) ? 1 : 0); else FLAGW_OF(0);
58		//FLAGW_AF(0);
59		for (shift = 1; shift <= cnt; shift++) {
60			FLAGW_CF(s & 1);

…Show last 41 lines

61			backup = s; //Save backup!
62			s = s >> 1;
63			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
64		}
65		flag_szp8((uint8_t)(s & 0xFF)); break;
66
67	case 7: //SAR r/m8
68		msb = s & 0x80;
69		//FLAGW_AF(0);
70		for (shift = 1; shift <= cnt; shift++) {
71			FLAGW_CF(s & 1);
72			backup = s; //Save backup!
73			s = (s >> 1) | msb;
74			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
75		}
76		byte tempSF;
77		tempSF = FLAG_SF; //Save the SF!
78		/*flag_szp8((uint8_t)(s & 0xFF));*/
79		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
80		if (!cnt) //Nothing done?
81		{
82			FLAGW_SF(tempSF); //We don't update when nothing's done!
83		}
84		else if (cnt==1) //Overflow is cleared on all 1-bit shifts!
85		{
86			flag_s8(s); //Affect sign as well!
87			FLAGW_OF(0); //Cleared!
88		}
89		else if (cnt) //Anything shifted at all?
90		{
91			flag_s8(s); //Affect sign as well!
92		}
93		if ((EMULATED_CPU>=CPU_NECV30) && cnt) //NECV20+ affected?
94		{
95			flag_p8(s); //Affect parity as well!
96		}
97		break;
98	}
99	op_grp2_cycles(cnt, varshift);
100	return(s & 0xFF);
101}

GRP2 16-bit

1word op_grp2_16(byte cnt, byte varshift) {
2	//uint32_t d,
3	INLINEREGISTER uint_32 s, shift, oldCF, msb;
4	//if (cnt>0x10) return(oper1); //NEC V20/V30+ limits shift count
5	if (EMULATED_CPU >= CPU_NECV30) cnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
6	word backup;
7	s = oper1;
8	oldCF = FLAG_CF;
9	switch (thereg) {
10	case 0: //ROL r/m16
11		for (shift = 1; shift <= cnt; shift++) {
12			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
13			s = s << 1;
14			s = s | FLAG_CF;
15		}
16		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 15) & 1));
17		break;
18
19	case 1: //ROR r/m16
20		for (shift = 1; shift <= cnt; shift++) {
21			FLAGW_CF(s & 1);
22			s = (s >> 1) | (FLAG_CF << 15);
23		}
24		if (cnt==1) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1));
25		break;
26
27	case 2: //RCL r/m16
28		for (shift = 1; shift <= cnt; shift++) {
29			oldCF = FLAG_CF;
30			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
31			s = s << 1;
32			s = s | oldCF;
33			//oldCF = ((s&0x8000)>>15)&1; //Save FLAG_CF!
34			//s = (s<<1)+FLAG_CF;
35			//FLAG_CF = oldCF;
36		}
37		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 15) & 1));
38		break;
39
40	case 3: //RCR r/m16
41		if (cnt==1) FLAGW_OF(((s >> 15) & 1) ^ FLAG_CF);
42		for (shift = 1; shift <= cnt; shift++) {
43			oldCF = FLAG_CF;
44			FLAGW_CF(s & 1);
45			s = (s >> 1) | (oldCF << 15);
46			//oldCF = s&1;
47			//s = (s<<1)+(FLAG_CF<<16);
48			//FLAG_CF = oldCF;
49		}
50		if (cnt==1) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1));
51		break;
52
53	case 4: case 6: //SHL r/m16
54		//FLAGW_AF(0);
55		for (shift = 1; shift <= cnt; shift++) {
56			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
57			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
58			s = (s << 1) & 0xFFFF;
59		}
60		if ((cnt) && (FLAG_CF == (s >> 15))) FLAGW_OF(0); else FLAGW_OF(1);

…Show last 49 lines

61		flag_szp16(s); break;
62
63	case 5: //SHR r/m16
64		if (cnt) FLAGW_OF((s & 0x8000) ? 1 : 0);
65		//FLAGW_AF(0);
66		for (shift = 1; shift <= cnt; shift++) {
67			FLAGW_CF(s & 1);
68			backup = s; //Save backup!
69			s = s >> 1;
70			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
71		}
72		flag_szp16(s); break;
73
74	case 7: //SAR r/m16
75		msb = s & 0x8000; //Read the MSB!
76		//FLAGW_AF(0);
77		for (shift = 1; shift <= cnt; shift++) {
78			FLAGW_CF(s & 1);
79			backup = s; //Save backup!
80			s = (s >> 1) | msb;
81			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
82		}
83		byte tempSF;
84		tempSF = FLAG_SF; //Save the SF!
85		/*flag_szp16(s);*/
86		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
87		if (!cnt) //Nothing done?
88		{
89			FLAGW_SF(tempSF); //We don't update when nothing's done!
90		}
91		else if (cnt==1) //Overflow is cleared on all 1-bit shifts!
92		{
93			flag_s16(s); //Affect sign as well!
94			FLAGW_OF(0); //Cleared!
95		}
96		else if (cnt) //Anything shifted at all?
97		{
98			flag_s16(s); //Affect sign as well!
99		}
100		if ((EMULATED_CPU>=CPU_NECV30) && cnt) //NECV20+ affected?
101		{
102			flag_p16(s); //Affect parity as well!
103			flag_s16(s); //Affect sign as well!
104		}
105		break;
106	}
107	op_grp2_cycles(cnt, varshift|4);
108	return(s & 0xFFFF);
109}

GRP2 32-bit:

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//uint32_t d,
3	INLINEREGISTER uint_32 s, shift, oldCF, msb;
4	//if (cnt>0x10) return(oper1d); //NEC V20/V30+ limits shift count
5	if (EMULATED_CPU >= CPU_NECV30) cnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
6	s = oper1d;
7	oldCF = FLAG_CF;
8	switch (thereg) {
9	case 0: //ROL r/m32
10		for (shift = 1; shift <= cnt; shift++) {
11			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
12			s = s << 1;
13			s = s | FLAG_CF;
14		}
15		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 31) & 1));
16		break;
17
18	case 1: //ROR r/m32
19		for (shift = 1; shift <= cnt; shift++) {
20			FLAGW_CF(s & 1);
21			s = (s >> 1) | (FLAG_CF << 31);
22		}
23		if (cnt==1) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
24		break;
25
26	case 2: //RCL r/m32
27		for (shift = 1; shift <= cnt; shift++) {
28			oldCF = FLAG_CF;
29			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
30			s = s << 1;
31			s = s | oldCF;
32			//oldCF = ((s&0x8000)>>15)&1; //Save FLAG_CF!
33			//s = (s<<1)+FLAG_CF;
34			//FLAG_CF = oldCF;
35		}
36		if (cnt==1) FLAGW_OF(FLAG_CF ^ ((s >> 31) & 1));
37		break;
38
39	case 3: //RCR r/m32
40		if (cnt==1) FLAGW_OF(((s >> 31) & 1) ^ FLAG_CF);
41		for (shift = 1; shift <= cnt; shift++) {
42			oldCF = FLAG_CF;
43			FLAGW_CF(s & 1);
44			s = (s >> 1) | (oldCF << 31);
45			//oldCF = s&1;
46			//s = (s<<1)+(FLAG_CF<<32);
47			//FLAG_CF = oldCF;
48		}
49		if (cnt==1) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
50		break;
51
52	case 4: case 6: //SHL r/m32
53		//FLAGW_AF(0);
54		for (shift = 1; shift <= cnt; shift++) {
55			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
56			s = (s << 1) & 0xFFFFFFFF;
57			//FLAGW_AF(1); //Auxiliary carry?
58		}
59		if ((cnt==1) && (FLAG_CF == (s >> 31))) FLAGW_OF(0); else FLAGW_OF(1);
60		flag_szp32(s); break;

…Show last 46 lines

61
62	case 5: //SHR r/m32
63		if (cnt==1) FLAGW_OF((s & 0x80000000) ? 1 : 0);
64		//FLAGW_AF(0);
65		for (shift = 1; shift <= cnt; shift++) {
66			FLAGW_CF(s & 1);
67			s = s >> 1;
68			//FLAGW_AF(1); //Auxiliary carry?
69		}
70		flag_szp32(s); break;
71
72	case 7: //SAR r/m32
73		msb = s & 0x80000000; //Read the MSB!
74		//FLAGW_AF(0);
75		for (shift = 1; shift <= cnt; shift++) {
76			FLAGW_CF(s & 1);
77			s = (s >> 1) | msb;
78			//FLAGW_AF(1); //Auxiliary carry?
79		}
80		byte tempSF;
81		tempSF = FLAG_SF; //Save the SF!
82		/*flag_szp32(s);*/
83		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
84		if (!cnt) //Nothing done?
85		{
86			FLAGW_SF(tempSF); //We don't update when nothing's done!
87		}
88		else if (cnt==1) //Overflow is cleared on all 1-bit shifts!
89		{
90			flag_s32(s); //Affect sign as well!
91			FLAGW_OF(0); //Cleared!
92		}
93		else if (cnt) //Anything shifted at all?
94		{
95			flag_s32(s); //Affect sign as well!
96		}
97		if ((EMULATED_CPU>=CPU_NECV30) && cnt) //NECV20+ affected?
98		{
99			flag_p32(s); //Affect parity as well!
100			flag_s32(s); //Affect sign as well!
101		}
102		break;
103	}
104	op_grp2_cycles32(cnt, varshift|4);
105	return(s & 0xFFFFFFFF);
106}

Anyone can see what's going wrong?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 3, by superfury

Posted on 2017-05-26, 09:15

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5912
Joined: 2014-03-08, 11:25
Location: Netherlands

I'm wondering about one thing, though: why is there a theoretical sal instruction? If there's a sar instruction(which shifts right, while keeping the sign bit), shouldn't there be a sal instruction for the same purpose? So each shift left shifts left, setting the most significant bit to the original sign(original bit 7, 15 or 31), thus making an effective SAL variant like SAR? Or is this impossible, due to the binary value being incompatible(needing to be negated+1 before and after shifting to be effective)?

Edit: So SAL X,n equals:
NEG X
SHL X,n
NEG X

Is that correct, or is that not needed for SAL X,1?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 2 of 3, by Jepael

Posted on 2017-05-26, 13:50

Jepael Offline

Rank Oldbie

Rank: Oldbie
Posts: 1195
Joined: 2005-06-15, 19:28
Location: Finland

superfury wrote:
I'm wondering about one thing, though: why is there a theoretical sal instruction?

That's because it's identical to shl, and both shl and sal gets assembled to same opcode, both assembler mnemonics exist for human convenience.

The second highest bit already matches the sign, unless the value is too big to shift and fit into result anyway.

Reply 3 of 3, by superfury

Posted on 2017-05-26, 16:32

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5912
Joined: 2014-03-08, 11:25
Location: Netherlands

There would be a problem when shifting left signed numbers: the sign bit(bit 7/15/31) would be shifted off (into carry(shifting 1) or nothingness with shifts larger than 1). So shifting left negative numbers might cause data loss? Or is this simply not the case(seeing as the negative number stays the same due to two's complement)? So FFFE(-2) becomes -4 because the high bits stay set(until the high bits overflow incorrectly when shifted off?)?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Go to top of page Go to top of page

Back to PC Emulation