test386.asm CPU tester

Reply 80 of 178, by superfury

Posted on 2017-11-05, 15:45

superfury Offline

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Rank: l33t++
Posts: 5910
Joined: 2014-03-08, 11:25
Location: Netherlands

This is what I've gotten so far:

16-bit:

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1b;
9	switch (thereg) {
10	case 0: //ROL r/m8
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			tempCF = ((s&0x80)>>7); //Save MSB!
15			s = (s << 1)|tempCF;
16		}
17		FLAGW_CF(s&1); //Set carry flag!
18		if (numcnt==1) FLAGW_OF(((s >> 7) & 1)^FLAG_CF);
19		break;
20
21	case 1: //ROR r/m8
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		for (shift = 1; shift <= numcnt; shift++) {
25			tempCF = (s&1); //Save LSB!
26			s = (s >> 1) | (tempCF << 7);
27		}
28		FLAGW_CF(((s&0x80)>>7)); //Set carry flag!
29		if (numcnt==1) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1));
30		break;
31
32	case 2: //RCL r/m8
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = ((s&0x80)>>7); //Save MSB!
37			s = (s << 1)|FLAG_CF; //Shift and set CF!
38			FLAGW_CF(tempCF); //Set CF!
39		}
40		if (numcnt==1) FLAGW_OF(((s >> 7) & 1)^FLAG_CF); //OF=MSB^CF
41		break;
42
43	case 3: //RCR r/m8
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
46		if (numcnt==1) FLAGW_OF((s >> 7) ^ FLAG_CF);
47		for (shift = 1; shift <= numcnt; shift++) {
48			tempCF = (s&1); //Save LSB!
49			s = (s >> 1) | (FLAG_CF << 7);
50			FLAGW_CF(tempCF);
51		}
52		break;
53
54	case 4: case 6: //SHL r/m8
55		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
56		//FLAGW_AF(0);
57		for (shift = 1; shift <= numcnt; shift++) {
58			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
59			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
60			s = (s << 1) & 0xFF;

…Show last 165 lines

61		}
62		if (numcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
63		if (numcnt) flag_szp8((uint8_t)(s&0xFF)); break;
64
65	case 5: //SHR r/m8
66		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
67		if (numcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
68		//FLAGW_AF(0);
69		for (shift = 1; shift <= numcnt; shift++) {
70			FLAGW_CF(s & 1);
71			//backup = s; //Save backup!
72			s = s >> 1;
73			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
74		}
75		if (numcnt) flag_szp8((uint8_t)(s & 0xFF)); break;
76
77	case 7: //SAR r/m8
78		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
79		msb = s & 0x80;
80		//FLAGW_AF(0);
81		for (shift = 1; shift <= numcnt; shift++) {
82			FLAGW_CF(s & 1);
83			//backup = s; //Save backup!
84			s = (s >> 1) | msb;
85			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
86		}
87		byte tempSF;
88		tempSF = FLAG_SF; //Save the SF!
89		/*flag_szp8((uint8_t)(s & 0xFF));*/
90		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
91		if (!numcnt) //Nothing done?
92		{
93			FLAGW_SF(tempSF); //We don't update when nothing's done!
94		}
95		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
96		{
97			flag_szp8(s); //Affect sign as well!
98			FLAGW_OF(0); //Cleared!
99		}
100		else if (numcnt) //Anything shifted at all?
101		{
102			flag_szp8(s); //Affect sign as well!
103			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
104			{
105				FLAGW_OF(0); //Cleared with count as well?
106			}
107		}
108		break;
109	}
110	op_grp2_cycles(numcnt, varshift);
111	return(s & 0xFF);
112}
113
114word op_grp2_16(byte cnt, byte varshift) {
115	//word d,
116	INLINEREGISTER uint_32 s, shift, tempCF, msb;
117	INLINEREGISTER byte numcnt;
118	//word backup;
119	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
120	numcnt = cnt; //Save count!
121	s = oper1;
122	switch (thereg) {
123	case 0: //ROL r/m16
124		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
125		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
126		for (shift = 1; shift <= numcnt; shift++) {
127			tempCF = ((s&0x8000)>>15); //Save MSB!
128			s = (s << 1)|tempCF;
129		}
130		FLAGW_CF(s&1); //Set carry flag!
131		if (numcnt==1) FLAGW_OF(((s >> 15) & 1)^FLAG_CF);
132		break;
133
134	case 1: //ROR r/m16
135		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
136		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
137		for (shift = 1; shift <= numcnt; shift++) {
138			tempCF = (s&1); //Save LSB!
139			s = (s >> 1) | (tempCF << 15);
140		}
141		FLAGW_CF(((s&0x8000)>>15)); //Set carry flag!
142		if (numcnt==1) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1));
143		break;
144
145	case 2: //RCL r/m16
146		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
147		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
148		for (shift = 1; shift <= numcnt; shift++) {
149			tempCF = ((s&0x8000)>>15); //Save MSB!
150			s = (s << 1)|FLAG_CF; //Shift and set CF!
151			FLAGW_CF(tempCF); //Set CF!
152		}
153		if (numcnt==1) FLAGW_OF(((s >> 15) & 1)^FLAG_CF); //OF=MSB^CF
154		break;
155
156	case 3: //RCR r/m16
157		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
158		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
159		if (numcnt==1) FLAGW_OF((s >> 15) ^ FLAG_CF);
160		for (shift = 1; shift <= numcnt; shift++) {
161			tempCF = (s&1); //Save LSB!
162			s = (s >> 1) | (FLAG_CF << 15);
163			FLAGW_CF(tempCF);
164		}
165		break;
166
167	case 4: case 6: //SHL r/m16
168		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
169		//FLAGW_AF(0);
170		for (shift = 1; shift <= numcnt; shift++) {
171			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
172			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
173			s = (s << 1) & 0xFFFF;
174		}
175		if (numcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
176		if (numcnt) flag_szp16((uint16_t)(s&0xFFFF)); break;
177
178	case 5: //SHR r/m16
179		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
180		if (numcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
181		//FLAGW_AF(0);
182		for (shift = 1; shift <= numcnt; shift++) {
183			FLAGW_CF(s & 1);
184			//backup = s; //Save backup!
185			s = s >> 1;
186			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
187		}
188		if (numcnt) flag_szp16((uint16_t)(s & 0xFFFF)); break;
189
190	case 7: //SAR r/m16
191		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
192		msb = s & 0x8000;
193		//FLAGW_AF(0);
194		for (shift = 1; shift <= numcnt; shift++) {
195			FLAGW_CF(s & 1);
196			//backup = s; //Save backup!
197			s = (s >> 1) | msb;
198			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
199		}
200		byte tempSF;
201		tempSF = FLAG_SF; //Save the SF!
202		/*flag_szp8((uint8_t)(s & 0xFF));*/
203		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
204		if (!numcnt) //Nothing done?
205		{
206			FLAGW_SF(tempSF); //We don't update when nothing's done!
207		}
208		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
209		{
210			flag_szp16(s); //Affect sign as well!
211			FLAGW_OF(0); //Cleared!
212		}
213		else if (numcnt) //Anything shifted at all?
214		{
215			flag_szp16(s); //Affect sign as well!
216			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
217			{
218				FLAGW_OF(0); //Cleared with count as well?
219			}
220		}
221		break;
222	}
223	op_grp2_cycles(numcnt, varshift);
224	return(s & 0xFFFF);
225}

32-bit:

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_64 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1d;
9	switch (thereg) {
10	case 0: //ROL r/m32
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			tempCF = ((s&0x80000000)>>31); //Save MSB!
15			s = (s << 1)|tempCF;
16		}
17		FLAGW_CF(s&1); //Set carry flag!
18		if (numcnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF);
19		break;
20
21	case 1: //ROR r/m32
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		for (shift = 1; shift <= numcnt; shift++) {
25			tempCF = (s&1); //Save LSB!
26			s = (s >> 1) | (tempCF << 31);
27		}
28		FLAGW_CF(((s&0x80000000)>>31)); //Set carry flag!
29		if (numcnt==1) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
30		break;
31
32	case 2: //RCL r/m32
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		for (shift = 1; shift <= numcnt; shift++) {
35			tempCF = ((s&0x80000000)>>31); //Save MSB!
36			s = (s << 1)|FLAG_CF; //Shift and set CF!
37			FLAGW_CF(tempCF); //Set CF!
38		}
39		if (numcnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF); //OF=MSB^CF
40		break;
41
42	case 3: //RCR r/m32
43		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
44		if (numcnt==1) FLAGW_OF((s >> 31) ^ FLAG_CF);
45		for (shift = 1; shift <= numcnt; shift++) {
46			tempCF = (s&1); //Save LSB!
47			s = (s >> 1) | (FLAG_CF << 31);
48			FLAGW_CF(tempCF);
49		}
50		break;
51
52	case 4: case 6: //SHL r/m32
53		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
54		//FLAGW_AF(0);
55		for (shift = 1; shift <= numcnt; shift++) {
56			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
57			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
58			s = (s << 1) & 0xFFFFFFFF;
59		}
60		if (numcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }

…Show last 50 lines

61		if (numcnt) flag_szp32((uint32_t)(s&0xFFFFFFFF)); break;
62
63	case 5: //SHR r/m32
64		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
65		if (numcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
66		//FLAGW_AF(0);
67		for (shift = 1; shift <= numcnt; shift++) {
68			FLAGW_CF(s & 1);
69			//backup = s; //Save backup!
70			s = s >> 1;
71			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
72		}
73		if (numcnt) flag_szp32((uint32_t)(s & 0xFFFFFFFF)); break;
74
75	case 7: //SAR r/m32
76		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
77		msb = s & 0x80000000;
78		//FLAGW_AF(0);
79		for (shift = 1; shift <= numcnt; shift++) {
80			FLAGW_CF(s & 1);
81			//backup = s; //Save backup!
82			s = (s >> 1) | msb;
83			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
84		}
85		byte tempSF;
86		tempSF = FLAG_SF; //Save the SF!
87		/*flag_szp8((uint8_t)(s & 0xFF));*/
88		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
89		if (!numcnt) //Nothing done?
90		{
91			FLAGW_SF(tempSF); //We don't update when nothing's done!
92		}
93		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
94		{
95			flag_szp32(s); //Affect sign as well!
96			FLAGW_OF(0); //Cleared!
97		}
98		else if (numcnt) //Anything shifted at all?
99		{
100			flag_szp32(s); //Affect sign as well!
101			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
102			{
103				FLAGW_OF(0); //Cleared with count as well?
104			}
105		}
106		break;
107	}
108	op_grp2_cycles32(numcnt, varshift);
109	return(s & 0xFFFFFFFF);
110}

There are still several things failing now(according to WinMerge, EDX/EAX is correct in all cases):
- ROLi B/W, ROLr, RORr: carry flag incorrectly set(set/not set)?
- RCLi B/W, RCRi B/W: missing Overflow flag set?
- RCRr: missing carry flag set(incorrectly)?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 81 of 178, by superfury

Posted on 2017-11-05, 18:25

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5910
Joined: 2014-03-08, 11:25
Location: Netherlands

I've tried behaviour like http://www.felixcloutier.com/x86/RCL:RCR:ROL:ROR.html , but whatever I do, it doesn't match the EE dump you've made?

This is my current code (SHL/SAL/SHR/SAR already checks out without errors now):

8/16-bit(8086+):

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1b;
9	switch (thereg) {
10	case 0: //ROL r/m8
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			tempCF = ((s&0x80)>>7); //Save MSB!
15			s = (s << 1)|tempCF;
16		}
17		FLAGW_CF(s&1); //Set carry flag!
18		if (numcnt) FLAGW_OF(((s >> 7) & 1)^FLAG_CF);
19		break;
20
21	case 1: //ROR r/m8
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		for (shift = 1; shift <= numcnt; shift++) {
25			tempCF = (s&1); //Save LSB!
26			s = (s >> 1) | (tempCF << 7);
27		}
28		FLAGW_CF(((s&0x80)>>7)); //Set carry flag!
29		if (varshift==0) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1));
30		break;
31
32	case 2: //RCL r/m8
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = ((s&0x80)>>7); //Save MSB!
37			s = (s << 1)|FLAG_CF; //Shift and set CF!
38			FLAGW_CF(tempCF); //Set CF!
39		}
40		if (varshift==0) FLAGW_OF(((s >> 7) & 1)^FLAG_CF); //OF=MSB^CF
41		break;
42
43	case 3: //RCR r/m8
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
46		if (varshift==0) FLAGW_OF((s >> 7) ^ FLAG_CF);
47		for (shift = 1; shift <= numcnt; shift++) {
48			tempCF = (s&1); //Save LSB!
49			s = (s >> 1) | (FLAG_CF << 7);
50			FLAGW_CF(tempCF);
51		}
52		break;
53
54	case 4: case 6: //SHL r/m8
55		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
56		//FLAGW_AF(0);
57		for (shift = 1; shift <= numcnt; shift++) {
58			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
59			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
60			s = (s << 1) & 0xFF;

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61		}
62		if (numcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
63		if (numcnt) flag_szp8((uint8_t)(s&0xFF)); break;
64
65	case 5: //SHR r/m8
66		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
67		if (numcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
68		//FLAGW_AF(0);
69		for (shift = 1; shift <= numcnt; shift++) {
70			FLAGW_CF(s & 1);
71			//backup = s; //Save backup!
72			s = s >> 1;
73			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
74		}
75		if (numcnt) flag_szp8((uint8_t)(s & 0xFF)); break;
76
77	case 7: //SAR r/m8
78		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
79		msb = s & 0x80;
80		//FLAGW_AF(0);
81		for (shift = 1; shift <= numcnt; shift++) {
82			FLAGW_CF(s & 1);
83			//backup = s; //Save backup!
84			s = (s >> 1) | msb;
85			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
86		}
87		byte tempSF;
88		tempSF = FLAG_SF; //Save the SF!
89		/*flag_szp8((uint8_t)(s & 0xFF));*/
90		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
91		if (!numcnt) //Nothing done?
92		{
93			FLAGW_SF(tempSF); //We don't update when nothing's done!
94		}
95		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
96		{
97			flag_szp8(s); //Affect sign as well!
98			FLAGW_OF(0); //Cleared!
99		}
100		else if (numcnt) //Anything shifted at all?
101		{
102			flag_szp8(s); //Affect sign as well!
103			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
104			{
105				FLAGW_OF(0); //Cleared with count as well?
106			}
107		}
108		break;
109	}
110	op_grp2_cycles(numcnt, varshift);
111	return(s & 0xFF);
112}
113
114word op_grp2_16(byte cnt, byte varshift) {
115	//word d,
116	INLINEREGISTER uint_32 s, shift, tempCF, msb;
117	INLINEREGISTER byte numcnt;
118	//word backup;
119	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
120	numcnt = cnt; //Save count!
121	s = oper1;
122	switch (thereg) {
123	case 0: //ROL r/m16
124		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
125		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
126		tempCF = 0;
127		for (shift = 1; shift <= numcnt; shift++) {
128			tempCF = ((s&0x8000)>>15); //Save MSB!
129			s = (s << 1)|tempCF;
130		}
131		FLAGW_CF(tempCF); //Set carry flag!
132		if (numcnt) FLAGW_OF(((s >> 15) & 1)^FLAG_CF);
133		break;
134
135	case 1: //ROR r/m16
136		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
137		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
138		for (shift = 1; shift <= numcnt; shift++) {
139			tempCF = (s&1); //Save LSB!
140			s = (s >> 1) | (tempCF << 15);
141		}
142		FLAGW_CF(((s&0x8000)>>15)); //Set carry flag!
143		if (varshift==0) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1));
144		break;
145
146	case 2: //RCL r/m16
147		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
148		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
149		for (shift = 1; shift <= numcnt; shift++) {
150			tempCF = ((s&0x8000)>>15); //Save MSB!
151			s = (s << 1)|FLAG_CF; //Shift and set CF!
152			FLAGW_CF(tempCF); //Set CF!
153		}
154		if (varshift==0) FLAGW_OF(((s >> 15) & 1)^FLAG_CF); //OF=MSB^CF
155		break;
156
157	case 3: //RCR r/m16
158		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
159		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
160		if (varshift==0) FLAGW_OF((s >> 15) ^ FLAG_CF);
161		for (shift = 1; shift <= numcnt; shift++) {
162			tempCF = (s&1); //Save LSB!
163			s = (s >> 1) | (FLAG_CF << 15);
164			FLAGW_CF(tempCF);
165		}
166		break;
167
168	case 4: case 6: //SHL r/m16
169		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
170		//FLAGW_AF(0);
171		for (shift = 1; shift <= numcnt; shift++) {
172			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
173			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
174			s = (s << 1) & 0xFFFF;
175		}
176		if (numcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
177		if (numcnt) flag_szp16((uint16_t)(s&0xFFFF)); break;
178
179	case 5: //SHR r/m16
180		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
181		if (numcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
182		//FLAGW_AF(0);
183		for (shift = 1; shift <= numcnt; shift++) {
184			FLAGW_CF(s & 1);
185			//backup = s; //Save backup!
186			s = s >> 1;
187			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
188		}
189		if (numcnt) flag_szp16((uint16_t)(s & 0xFFFF)); break;
190
191	case 7: //SAR r/m16
192		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
193		msb = s & 0x8000;
194		//FLAGW_AF(0);
195		for (shift = 1; shift <= numcnt; shift++) {
196			FLAGW_CF(s & 1);
197			//backup = s; //Save backup!
198			s = (s >> 1) | msb;
199			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
200		}
201		byte tempSF;
202		tempSF = FLAG_SF; //Save the SF!
203		/*flag_szp8((uint8_t)(s & 0xFF));*/
204		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
205		if (!numcnt) //Nothing done?
206		{
207			FLAGW_SF(tempSF); //We don't update when nothing's done!
208		}
209		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
210		{
211			flag_szp16(s); //Affect sign as well!
212			FLAGW_OF(0); //Cleared!
213		}
214		else if (numcnt) //Anything shifted at all?
215		{
216			flag_szp16(s); //Affect sign as well!
217			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
218			{
219				FLAGW_OF(0); //Cleared with count as well?
220			}
221		}
222		break;
223	}
224	op_grp2_cycles(numcnt, varshift);
225	return(s & 0xFFFF);
226}

32-bit:

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_64 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1d;
9	switch (thereg) {
10	case 0: //ROL r/m32
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		tempCF = 0;
14		for (shift = 1; shift <= numcnt; shift++) {
15			tempCF = ((s&0x80000000)>>31); //Save MSB!
16			s = (s << 1)|tempCF;
17		}
18		FLAGW_CF(tempCF); //Set carry flag!
19		if (numcnt) FLAGW_OF(((s >> 31) & 1)^FLAG_CF);
20		break;
21
22	case 1: //ROR r/m32
23		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
24		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
25		for (shift = 1; shift <= numcnt; shift++) {
26			tempCF = (s&1); //Save LSB!
27			s = (s >> 1) | (tempCF << 31);
28		}
29		FLAGW_CF(((s&0x80000000)>>31)); //Set carry flag!
30		if (varshift==0) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
31		break;
32
33	case 2: //RCL r/m32
34		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = ((s&0x80000000)>>31); //Save MSB!
37			s = (s << 1)|FLAG_CF; //Shift and set CF!
38			FLAGW_CF(tempCF); //Set CF!
39		}
40		if (varshift==0) FLAGW_OF(((s >> 31) & 1)^FLAG_CF); //OF=MSB^CF
41		break;
42
43	case 3: //RCR r/m32
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (varshift==0) FLAGW_OF((s >> 31) ^ FLAG_CF);
46		for (shift = 1; shift <= numcnt; shift++) {
47			tempCF = (s&1); //Save LSB!
48			s = (s >> 1) | (FLAG_CF << 31);
49			FLAGW_CF(tempCF);
50		}
51		break;
52
53	case 4: case 6: //SHL r/m32
54		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
55		//FLAGW_AF(0);
56		for (shift = 1; shift <= numcnt; shift++) {
57			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
58			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
59			s = (s << 1) & 0xFFFFFFFF;
60		}

…Show last 51 lines

61		if (numcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }
62		if (numcnt) flag_szp32((uint32_t)(s&0xFFFFFFFF)); break;
63
64	case 5: //SHR r/m32
65		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
66		if (numcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
67		//FLAGW_AF(0);
68		for (shift = 1; shift <= numcnt; shift++) {
69			FLAGW_CF(s & 1);
70			//backup = s; //Save backup!
71			s = s >> 1;
72			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
73		}
74		if (numcnt) flag_szp32((uint32_t)(s & 0xFFFFFFFF)); break;
75
76	case 7: //SAR r/m32
77		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
78		msb = s & 0x80000000;
79		//FLAGW_AF(0);
80		for (shift = 1; shift <= numcnt; shift++) {
81			FLAGW_CF(s & 1);
82			//backup = s; //Save backup!
83			s = (s >> 1) | msb;
84			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
85		}
86		byte tempSF;
87		tempSF = FLAG_SF; //Save the SF!
88		/*flag_szp8((uint8_t)(s & 0xFF));*/
89		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
90		if (!numcnt) //Nothing done?
91		{
92			FLAGW_SF(tempSF); //We don't update when nothing's done!
93		}
94		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
95		{
96			flag_szp32(s); //Affect sign as well!
97			FLAGW_OF(0); //Cleared!
98		}
99		else if (numcnt) //Anything shifted at all?
100		{
101			flag_szp32(s); //Affect sign as well!
102			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
103			{
104				FLAGW_OF(0); //Cleared with count as well?
105			}
106		}
107		break;
108	}
109	op_grp2_cycles32(numcnt, varshift);
110	return(s & 0xFFFFFFFF);
111}

Can anyone help me getting this bug-free?

Edit: Implemented the version from fake86/cape, but still not checking out correctly? IMUL8/16/32 also still fails(wrong results?)?

Shift opcodes found at(16-bit/8-bit): https://bitbucket.org/superfury/unipcemu/src/ … 086.c?at=master
Opcodes 69/6B 16-bit and Shift extension opcodes C0/C1: https://bitbucket.org/superfury/unipcemu/src/ … V30.c?at=master
32-bit extensions: https://bitbucket.org/superfury/unipcemu/src/ … 386.c?at=master

Look for OP6B/OP69(NEC V30&386) and grp2_8/grp2_16/grp2_32(in 386, others in 8086(partial called by instruction set extensions in NEC V30(186+) as well)).

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 82 of 178, by superfury

Posted on 2017-11-06, 14:07

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5910
Joined: 2014-03-08, 11:25
Location: Netherlands

I've redirected all x86 IMUL instructions(except the GRP opcodes) to the following general function(since it's the same for opcodes 69/6B and 0FAF). I also fixed some stage problems(different execution stages(fetch phase(two subphases fetching r/m), execution phase, result phase)), which were causing part of the problems.

All IMUL C-style(69/6A/0FAF) execution phases are now handled by the following function:

1void CPU_CIMUL(uint_32 base, byte basesize, uint_32 multiplicant, byte multiplicantsize, uint_32 *result, byte resultsize)
2{
3	temp1.val64 = signextend64(base,basesize); //Read reg instead! Word register = Word register * imm16!
4	temp2.val64 = signextend64(multiplicant,multiplicantsize); //Immediate word is second/third parameter!
5	temp3.val64s = temp1.val64s; //Load and...
6	temp3.val64s *= temp2.val64s; //Signed multiplication!
7	temp2.val64 = signextend64(temp3.val64,resultsize); //For checking for overflow and giving the correct result!
8	if (temp3.val64s==temp2.val64s) FLAGW_OF(0); //Overflow flag is cleared when high word is a sign extension of the low word(values are equal)!
9	else FLAGW_OF(1);
10	FLAGW_CF(FLAG_OF); //OF=CF!
11	FLAGW_SF((temp3.val64&0x8000000000000000)>>63); //Sign!
12	FLAGW_PF(parity[temp3.val16&0xFF]); //Parity flag!
13	FLAGW_ZF((temp3.val64==0)?1:0); //Set the zero flag!	
14	*result = (uint_32)temp2.val64; //Save the result, truncated to used size as 64-bit sign extension!
15}

IMUL8 B/W execute correctly.
IMUL8 D fails with incorrect results?
IMUL16 W/D executes correctly.
IMUL32 D executes correctly.

FOr some reason, only the IMUL8 D fails? I only have four implementations of those IMUL instructions: r/m16,imm8; r/m32,imm16; r/m16,imm16 and r/m32,imm32. Am I supposed to believe there's another variant of that one I don't know of? There are supposed to be only four variants, which are made using the two opcodes(69/6B) and operand size(16-bit vs 32-bit)? What is the fifth variant?

Edit: These are my IMUL variants(16-bit as NECV30+, 32-bit as 386):
16-bit:
Opcode 69h 16-bit:

1extern uint_32 IMULresult; //Buffer to use, general purpose!
2extern word instructionbufferw, instructionbufferw2; //For 16-bit read storage!
3void CPU186_OP69()
4{
5	memcpy(&info,&params.info[MODRM_src0],sizeof(info)); //Reg!
6	memcpy(&info2,&params.info[MODRM_src1],sizeof(info2)); //Second parameter(R/M)!
7	if (MODRM_MOD(params.modrm)==3) //Two-operand version?
8	{
9		debugger_setcommand("IMUL %s,%04X",info.text,immw); //IMUL reg,imm16
10	}
11	else //Three-operand version?
12	{
13		debugger_setcommand("IMUL %s,%s,%04X",info.text,info2.text,immw); //IMUL reg,r/m16,imm16
14	}
15	if (CPU[activeCPU].instructionstep==0) //First step?
16	{
17		/*
18		if (MODRM_MOD(params.modrm)!=3) //Use R/M to calculate the result(Three-operand version)?
19		{
20		*/
21			if (modrm_check16(&params,1,1)) return; //Abort on fault!
22			if (CPU8086_internal_stepreadmodrmw(0,&instructionbufferw,MODRM_src1)) return; //Read R/M!
23			temp1.val16high = 0; //Clear high part by default!
24		/*}
25		else
26		{
27			if (CPU8086_instructionstepreadmodrmw(0,&temp1.val16,0)) return; //Read reg instead! Word register = Word register * imm16!
28			temp1.val16high = 0; //Clear high part by default!
29		}
30		*/
31		++CPU[activeCPU].instructionstep; //Next step!
32	}
33	if (CPU[activeCPU].instructionstep==1) //Second step?
34	{
35		CPU_CIMUL(instructionbufferw,16,immw,16,&IMULresult,16); //Immediate word is second/third parameter!
36		CPU_apply286cycles(); //Apply the 80286+ cycles!
37		//We're writing to the register always, so no normal writeback!
38		++CPU[activeCPU].instructionstep; //Next step!
39	}
40	modrm_write16(&params,MODRM_src0,(IMULresult&0xFFFF),0); //Write to the destination(register)!
41}

Opcode 6Bh 16-bit:

1void CPU186_OP6B()
2{
3	memcpy(&info,&params.info[MODRM_src0],sizeof(info)); //Reg!
4	memcpy(&info2,&params.info[MODRM_src1],sizeof(info2)); //Second parameter(R/M)!
5	/*
6	if (MODRM_MOD(params.modrm)==3) //Two-operand version?
7	{
8		debugger_setcommand("IMUL %s,%02X",info.text,immb); //IMUL reg,imm8
9	}
10	else //Three-operand version?
11	{
12	*/
13		debugger_setcommand("IMUL %s,%s,%02X",info.text,info2.text,immb); //IMUL reg,r/m16,imm8
14	//}
15
16	if (CPU[activeCPU].instructionstep==0) //First step?
17	{
18		/*if (MODRM_MOD(params.modrm)!=3) //Use R/M to calculate the result(Three-operand version)?
19		{
20		*/
21			if (modrm_check16(&params,1,1)) return; //Abort on fault!
22			if (CPU8086_internal_stepreadmodrmw(0,&instructionbufferw,MODRM_src1)) return; //Read R/M!
23			temp1.val16high = 0; //Clear high part by default!
24		/*}
25		else
26		{
27			if (CPU8086_instructionstepreadmodrmw(0,&temp1.val16,MODRM_src0)) return; //Read reg instead! Word register = Word register * imm16!
28			temp1.val16high = 0; //Clear high part by default!
29		}
30		*/
31		++CPU[activeCPU].instructionstep; //Next step!
32	}
33	if (CPU[activeCPU].instructionstep==1) //Second step?
34	{
35		CPU_CIMUL(instructionbufferw,16,immb,8,&IMULresult,16); //Immediate word is second/third parameter!
36		CPU_apply286cycles(); //Apply the 80286+ cycles!
37		//We're writing to the register always, so no normal writeback!
38		++CPU[activeCPU].instructionstep; //Next step!
39	}
40
41	modrm_write16(&params,MODRM_src0,(IMULresult&0xFFFF),0); //Write to register!
42}

Opcode 69h 32-bit:

1void CPU386_OP69()
2{
3	memcpy(&info,&params.info[MODRM_src0],sizeof(info)); //Reg!
4	memcpy(&info2,&params.info[MODRM_src1],sizeof(info2)); //Second parameter(R/M)!
5	/*
6	if (MODRM_MOD(params.modrm)==3) //Two-operand version?
7	{
8		debugger_setcommand("IMUL %s,%08X",info.text,imm32); //IMUL reg,imm32
9	}
10	else //Three-operand version?
11	{
12	*/
13		debugger_setcommand("IMUL %s,%s,%08X",info.text,info2.text,imm32); //IMUL reg,r/m32,imm32
14	//}
15	if (CPU[activeCPU].instructionstep==0) //First step?
16	{
17		/*if (MODRM_MOD(params.modrm)!=3) //Use R/M to calculate the result(Three-operand version)?
18		{
19		*/
20			if (modrm_check32(&params,1,1)) return; //Abort on fault!
21			if (CPU80386_internal_stepreadmodrmdw(0,&instructionbufferd,MODRM_src1)) return; //Read R/M!
22			temp1.val32high = 0; //Clear high part by default!
23		/*}
24		else
25		{
26			if (CPU80386_instructionstepreadmodrmdw(0,&temp1.val32,0)) return; //Read reg instead! Word register = Word register * imm32!
27			temp1.val32high = 0; //Clear high part by default!
28		}
29		*/
30		++CPU[activeCPU].instructionstep; //Next step!
31	}
32	if (CPU[activeCPU].instructionstep==1) //Second step?
33	{
34		CPU_CIMUL(instructionbufferd,32,imm32,32,&IMULresult,32); //Execute!
35		CPU_apply286cycles(); //Apply the 80286+ cycles!
36		//We're writing to the register always, so no normal writeback!
37		++CPU[activeCPU].instructionstep; //Next step!
38	}
39	modrm_write32(&params,MODRM_src0,IMULresult); //Write to the destination(register)!
40}

Opcode 6Bh 32-bit:

1void CPU386_OP6B()
2{
3	memcpy(&info,&params.info[MODRM_src0],sizeof(info)); //Reg!
4	memcpy(&info2,&params.info[MODRM_src1],sizeof(info2)); //Second parameter(R/M)!
5	/*
6	if (MODRM_MOD(params.modrm)==3) //Two-operand version?
7	{
8		debugger_setcommand("IMUL %s,%02X",info.text,immb); //IMUL reg,imm8
9	}
10	else //Three-operand version?
11	{
12	*/
13		debugger_setcommand("IMUL %s,%s,%02X",info.text,info2.text,immb); //IMUL reg,r/m32,imm8
14	//}
15
16	if (CPU[activeCPU].instructionstep==0) //First step?
17	{
18		/*if (MODRM_MOD(params.modrm)!=3) //Use R/M to calculate the result(Three-operand version)?
19		{
20		*/
21			if (modrm_check32(&params,1,1)) return; //Abort on fault!
22			if (CPU80386_internal_stepreadmodrmdw(0,&instructionbufferd,MODRM_src1)) return; //Read R/M!
23			temp1.val32high = 0; //Clear high part by default!
24		/*}
25		else
26		{
27			if (CPU80386_instructionstepreadmodrmdw(0,&temp1.val32,MODRM_src0)) return; //Read reg instead! Word register = Word register * imm32!
28			temp1.val32high = 0; //Clear high part by default!
29		}
30		*/
31		++CPU[activeCPU].instructionstep; //Next step!
32	}
33	if (CPU[activeCPU].instructionstep==1) //Second step?
34	{
35		CPU_CIMUL(instructionbufferd,32,immb,8,&IMULresult,32); //Execute!
36		CPU_apply286cycles(); //Apply the 80286+ cycles!
37		//We're writing to the register always, so no normal writeback!
38		++CPU[activeCPU].instructionstep; //Next step!
39	}
40
41	modrm_write32(&params,MODRM_src0,IMULresult); //Write to register!
42}

Edit: After having fixed the 32-bit instruction tables(which determine things like modR/M parameter order(MODRM_src0/1 in this case too)), I noticed that the ModR/M parameter order was correct in the 16-bit case, but REVERSED in the 32-bit case! 😖 After having fixed those, all IMUL tests check out correctly without bugs. 😁

Now the only problems left are (according to the testsuite) the rotate instructions(ROL/ROR/RCL/RCR)? It currently follows the logic like fake86 and CAPE, but it seems those are incorrect somehow? Both flags(carry flags and overflow flags) and results don't match up with the EE reference?

The attachment porte9.log is no longer available

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Reply 83 of 178, by peterferrie

Posted on 2017-11-06, 23:24

peterferrie Offline

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It might help if you gave some specific examples of values that are failing tests. Then I can look at the code and follow the flow to find the problem.

Reply 84 of 178, by superfury

Posted on 2017-11-07, 06:17

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Simply diff the porte9.log against the EE reference log of test386.asm?

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Reply 85 of 178, by superfury

Posted on 2017-11-07, 10:32

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Just made a simple diff using diff from the diffutils for Windows:

The attachment test386-EE-reference.diff is no longer available

Anyone can see what's going wrong? It's using the same algorithm as fake86 and CAPE(at least for the ROL/ROR/RCL/RCR instructions. SHL/SAL/SHR instructions are modfied to give correct results).

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1b;
9	tempCF = FLAG_CF; //Save CF!
10	switch (thereg) {
11	case 0: //ROL r/m8
12		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
13		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
14		for (shift = 1; shift <= numcnt; shift++) {
15			FLAGW_CF((s&0x80)>>7); //Save MSB!
16			s = (s << 1)|FLAG_CF;
17		}
18		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //Only when not using CL?
19		break;
20
21	case 1: //ROR r/m8
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		tempCF = FLAG_CF; //Default: unchanged!
25		for (shift = 1; shift <= numcnt; shift++) {
26			FLAGW_CF(s&1); //Save LSB!
27			s = (s >> 1) | (FLAG_CF << 7);
28		}
29		if (varshift==0) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1)); //Only when not using CL?
30		break;
31
32	case 2: //RCL r/m8
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = FLAG_CF;
37			FLAGW_CF((s&0x80)>>7); //Save MSB!
38			s = (s << 1)|tempCF; //Shift and set CF!
39		}
40		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //OF=MSB^CF, only when not using CL?
41		break;
42
43	case 3: //RCR r/m8
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
46		if (numcnt==1) FLAGW_OF( FLAG_CF^(s >> 7));
47		for (shift = 1; shift <= numcnt; shift++) {
48			tempCF = FLAG_CF;
49			FLAGW_CF(s&1); //Save LSB!
50			s = (s >> 1) | (tempCF << 7);
51		}
52		break;
53
54	case 4: case 6: //SHL r/m8
55		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
56		//FLAGW_AF(0);
57		for (shift = 1; shift <= numcnt; shift++) {
58			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
59			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
60			s = (s << 1) & 0xFF;

…Show last 275 lines

61		}
62		if (numcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
63		if (numcnt) flag_szp8((uint8_t)(s&0xFF)); break;
64
65	case 5: //SHR r/m8
66		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
67		if (numcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
68		//FLAGW_AF(0);
69		for (shift = 1; shift <= numcnt; shift++) {
70			FLAGW_CF(s & 1);
71			//backup = s; //Save backup!
72			s = s >> 1;
73			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
74		}
75		if (numcnt) flag_szp8((uint8_t)(s & 0xFF)); break;
76
77	case 7: //SAR r/m8
78		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
79		msb = s & 0x80;
80		//FLAGW_AF(0);
81		for (shift = 1; shift <= numcnt; shift++) {
82			FLAGW_CF(s & 1);
83			//backup = s; //Save backup!
84			s = (s >> 1) | msb;
85			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
86		}
87		byte tempSF;
88		tempSF = FLAG_SF; //Save the SF!
89		/*flag_szp8((uint8_t)(s & 0xFF));*/
90		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
91		if (!numcnt) //Nothing done?
92		{
93			FLAGW_SF(tempSF); //We don't update when nothing's done!
94		}
95		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
96		{
97			flag_szp8(s); //Affect sign as well!
98			FLAGW_OF(0); //Cleared!
99		}
100		else if (numcnt) //Anything shifted at all?
101		{
102			flag_szp8(s); //Affect sign as well!
103			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
104			{
105				FLAGW_OF(0); //Cleared with count as well?
106			}
107		}
108		break;
109	}
110	op_grp2_cycles(numcnt, varshift);
111	return(s & 0xFF);
112}
113
114word op_grp2_16(byte cnt, byte varshift) {
115	//word d,
116	INLINEREGISTER uint_32 s, shift, tempCF, msb;
117	INLINEREGISTER byte numcnt;
118	//word backup;
119	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
120	numcnt = cnt; //Save count!
121	s = oper1;
122	tempCF = FLAG_CF; //Save CF!
123	switch (thereg) {
124	case 0: //ROL r/m16
125		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
126		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
127		for (shift = 1; shift <= numcnt; shift++) {
128			FLAGW_CF((s&0x8000)>>15); //Save MSB!
129			s = (s << 1)|FLAG_CF;
130		}
131		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //Only when not using CL?
132		break;
133
134	case 1: //ROR r/m16
135		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
136		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
137		tempCF = FLAG_CF; //Default: unchanged!
138		for (shift = 1; shift <= numcnt; shift++) {
139			FLAGW_CF(s&1); //Save LSB!
140			s = (s >> 1) | (FLAG_CF << 15);
141		}
142		if (varshift==0) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1)); //Only when not using CL?
143		break;
144
145	case 2: //RCL r/m16
146		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
147		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
148		for (shift = 1; shift <= numcnt; shift++) {
149			tempCF = FLAG_CF;
150			FLAGW_CF((s&0x8000)>>15); //Save MSB!
151			s = (s << 1)|tempCF; //Shift and set CF!
152		}
153		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //OF=MSB^CF, only when not using CL?
154		break;
155
156	case 3: //RCR r/m16
157		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
158		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
159		if (numcnt==1) FLAGW_OF(FLAG_CF^(s >> 15));
160		for (shift = 1; shift <= numcnt; shift++) {
161			tempCF = FLAG_CF;
162			FLAGW_CF(s&1); //Save LSB!
163			s = (s >> 1) | (tempCF << 15);
164		}
165		break;
166
167	case 4: case 6: //SHL r/m16
168		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
169		//FLAGW_AF(0);
170		for (shift = 1; shift <= numcnt; shift++) {
171			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
172			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
173			s = (s << 1) & 0xFFFF;
174		}
175		if (numcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
176		if (numcnt) flag_szp16((uint16_t)(s&0xFFFF)); break;
177
178	case 5: //SHR r/m16
179		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
180		if (numcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
181		//FLAGW_AF(0);
182		for (shift = 1; shift <= numcnt; shift++) {
183			FLAGW_CF(s & 1);
184			//backup = s; //Save backup!
185			s = s >> 1;
186			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
187		}
188		if (numcnt) flag_szp16((uint16_t)(s & 0xFFFF)); break;
189
190	case 7: //SAR r/m16
191		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
192		msb = s & 0x8000;
193		//FLAGW_AF(0);
194		for (shift = 1; shift <= numcnt; shift++) {
195			FLAGW_CF(s & 1);
196			//backup = s; //Save backup!
197			s = (s >> 1) | msb;
198			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
199		}
200		byte tempSF;
201		tempSF = FLAG_SF; //Save the SF!
202		/*flag_szp8((uint8_t)(s & 0xFF));*/
203		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
204		if (!numcnt) //Nothing done?
205		{
206			FLAGW_SF(tempSF); //We don't update when nothing's done!
207		}
208		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
209		{
210			flag_szp16(s); //Affect sign as well!
211			FLAGW_OF(0); //Cleared!
212		}
213		else if (numcnt) //Anything shifted at all?
214		{
215			flag_szp16(s); //Affect sign as well!
216			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
217			{
218				FLAGW_OF(0); //Cleared with count as well?
219			}
220		}
221		break;
222	}
223	op_grp2_cycles(numcnt, varshift);
224	return(s & 0xFFFF);
225}
226
227uint_32 op_grp2_32(byte cnt, byte varshift) {
228	//word d,
229	INLINEREGISTER uint_64 s, shift, tempCF, msb;
230	INLINEREGISTER byte numcnt;
231	//word backup;
232	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
233	numcnt = cnt; //Save count!
234	s = oper1d;
235	switch (thereg) {
236	case 0: //ROL r/m32
237		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
238		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
239		for (shift = 1; shift <= numcnt; shift++) {
240			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
241			s = (s << 1)|FLAG_CF;
242		}
243		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 31) & 1));
244		break;
245
246	case 1: //ROR r/m32
247		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
248		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
249		tempCF = FLAG_CF; //Default: unchanged!
250		for (shift = 1; shift <= numcnt; shift++) {
251			FLAGW_CF(s&1); //Save LSB!
252			s = (s >> 1) | (FLAG_CF << 31);
253		}
254		if (varshift==0) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
255		break;
256
257	case 2: //RCL r/m32
258		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
259		for (shift = 1; shift <= numcnt; shift++) {
260			tempCF = FLAG_CF;
261			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
262			s = (s << 1)|tempCF; //Shift and set CF!
263		}
264		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 31) & 1)); //OF=MSB^CF
265		break;
266
267	case 3: //RCR r/m32
268		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
269		if (numcnt==1) FLAGW_OF(FLAG_CF^(s >> 31));
270		for (shift = 1; shift <= numcnt; shift++) {
271			tempCF = FLAG_CF;
272			FLAGW_CF(s&1); //Save LSB!
273			s = (s >> 1) | (tempCF << 31);
274		}
275		break;
276
277	case 4: case 6: //SHL r/m32
278		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
279		//FLAGW_AF(0);
280		for (shift = 1; shift <= numcnt; shift++) {
281			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
282			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
283			s = (s << 1) & 0xFFFFFFFF;
284		}
285		if (numcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }
286		if (numcnt) flag_szp32((uint32_t)(s&0xFFFFFFFF)); break;
287
288	case 5: //SHR r/m32
289		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
290		if (numcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
291		//FLAGW_AF(0);
292		for (shift = 1; shift <= numcnt; shift++) {
293			FLAGW_CF(s & 1);
294			//backup = s; //Save backup!
295			s = s >> 1;
296			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
297		}
298		if (numcnt) flag_szp32((uint32_t)(s & 0xFFFFFFFF)); break;
299
300	case 7: //SAR r/m32
301		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
302		msb = s & 0x80000000;
303		//FLAGW_AF(0);
304		for (shift = 1; shift <= numcnt; shift++) {
305			FLAGW_CF(s & 1);
306			//backup = s; //Save backup!
307			s = (s >> 1) | msb;
308			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
309		}
310		byte tempSF;
311		tempSF = FLAG_SF; //Save the SF!
312		/*flag_szp8((uint8_t)(s & 0xFF));*/
313		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
314		if (!numcnt) //Nothing done?
315		{
316			FLAGW_SF(tempSF); //We don't update when nothing's done!
317		}
318		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
319		{
320			flag_szp32(s); //Affect sign as well!
321			FLAGW_OF(0); //Cleared!
322		}
323		else if (numcnt) //Anything shifted at all?
324		{
325			flag_szp32(s); //Affect sign as well!
326			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
327			{
328				FLAGW_OF(0); //Cleared with count as well?
329			}
330		}
331		break;
332	}
333	op_grp2_cycles32(numcnt, varshift);
334	return(s & 0xFFFFFFFF);
335}

The cnt is CL or 1, varshift determines the instruction that's used(Opcodes D0/D1 uses 0(reg/mem with 1 shift), Opcodes D2/D3 uses 1(reg/mem with variable shift), Opcodes C0/C1 uses 2(reg/mem with immediate variable)).

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Reply 86 of 178, by superfury

Posted on 2017-11-08, 13:53

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Just tried running MS-DOS 6.22's EMM386.EXE with HIMEM.SYS on MS-DOS 5.0a. I now see it's trying to execute a #PF handler due to some unpaged memory, which eventually causes a #GP handler due to EBX offset calculation overflowing(32-bit offset using 16-bit DS descriptor), which eventually runs into unpaged memory causing the previously #PF handler to fire again nested. This repeats infinitely?

The attachment debugger.log is no longer available

I also see something odd: lots of newlines in the debugger log that shouldn't actually be there? Strange... Also, the strange register state of that MOV instruction that's #GP faulting?

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Reply 87 of 178, by peterferrie

Posted on 2017-11-08, 18:41

peterferrie Offline

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Your registers contain text strings "0012", "C7CA", "=00(". I suggest that you go back a bit to see how they acquired such values.

Reply 88 of 178, by vladstamate

Posted on 2017-11-08, 19:20

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Maybe they are trying to speak and tell us something.... 😀))

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Reply 89 of 178, by superfury

Posted on 2017-11-08, 21:14

superfury Offline

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I know that the debugger unit in UniPCemu has such texts(Logging of memory accesses use "%08X=%02X(%c)" with values memaddr, value, value in a sprintf)? Maybe rogue memory(overflow) logs somehow?

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Reply 90 of 178, by superfury

Posted on 2017-11-09, 19:35

superfury Offline

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One thing that still goes awry is the ROR instruction?

1RORi D EAX=00000001 EDX=00000000 PS=0044 EAX=FE000000 EDX=00000000 PS=0044

Anyone? EAX is supposed to be 02000000?

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Reply 91 of 178, by vladstamate

Posted on 2017-11-09, 19:43

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I finally got CAPE to reach 0xE0 test step in test386.asm. Once I reach where you are now, I can compare our results.

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Reply 92 of 178, by superfury

Posted on 2017-11-09, 23:33

superfury Offline

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In the meanwhile fixed some bugs and some instruction debugging(opcodes 05h, 0Dh and C0h still were adding the operand size suffixes(now handled by the modr/m)). That should make it fully common log format compatible again.

Btw, the short method of memory accesses is currently used with UniPCemu's common log format register logs(see the post giving an example). Don't know if you've implemented that yet(since your webpage still doesn't mention memory transactions).

I've also fixed some compatibility differences between the GRP2 opcodes, which now handle the shifts/rotates in roughly the same way(still centered around the op_grp2_8/16/32, but the surrounding logic has been generalized for all those instructions(each opcode adjusted for the same method of handling data)).

One little warning, though: even in the compact common log format it still ammounts to a huge log when running that BIOS. Especially the POST EE logs take quite a few GB of logging data(last time it was about 19GB in total, making it practically impossible to open without hanging Windows 10, even with a good gaming PC as mine(with a i7-4790K@4.0GHz CPU and 8GB RAM)).

I've also rechecked my GRP2(shift/rotate) emulation, but looking at the logic to be executed no such strange behaviour should be present? The rotates with and without carry shouldn't give any strange data(EAX/EDX) results like 0xFE000000 instead of 0x02000000. It seems to have filled bits 31-30 with 1 bits for some odd reason?

My current GRP2 32-bit emulation:

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_64 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1d;
9	switch (thereg) {
10	case 0: //ROL r/m32
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
15			s = (s << 1)|FLAG_CF;
16		}
17		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 31) & 1));
18		break;
19
20	case 1: //ROR r/m32
21		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
22		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
23		tempCF = FLAG_CF; //Default: unchanged!
24		for (shift = 1; shift <= numcnt; shift++) {
25			FLAGW_CF(s&1); //Save LSB!
26			s = (s >> 1) | (FLAG_CF << 31);
27		}
28		if (varshift==0) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
29		break;
30
31	case 2: //RCL r/m32
32		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
33		for (shift = 1; shift <= numcnt; shift++) {
34			tempCF = FLAG_CF;
35			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
36			s = (s << 1)|tempCF; //Shift and set CF!
37		}
38		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 31) & 1)); //OF=MSB^CF
39		break;
40
41	case 3: //RCR r/m32
42		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
43		if (numcnt==1) FLAGW_OF(FLAG_CF^(s >> 31));
44		for (shift = 1; shift <= numcnt; shift++) {
45			tempCF = FLAG_CF;
46			FLAGW_CF(s&1); //Save LSB!
47			s = (s >> 1) | (tempCF << 31);
48		}
49		break;
50
51	case 4: case 6: //SHL r/m32
52		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
53		//FLAGW_AF(0);
54		for (shift = 1; shift <= numcnt; shift++) {
55			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
56			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
57			s = (s << 1) & 0xFFFFFFFF;
58		}
59		if (numcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }
60		if (numcnt) flag_szp32((uint32_t)(s&0xFFFFFFFF));

…Show last 51 lines

61		break;
62
63	case 5: //SHR r/m32
64		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
65		if (numcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
66		//FLAGW_AF(0);
67		for (shift = 1; shift <= numcnt; shift++) {
68			FLAGW_CF(s & 1);
69			//backup = s; //Save backup!
70			s = s >> 1;
71			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
72		}
73		if (numcnt) flag_szp32((uint32_t)(s & 0xFFFFFFFF));
74		break;
75
76	case 7: //SAR r/m32
77		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
78		msb = s & 0x80000000;
79		//FLAGW_AF(0);
80		for (shift = 1; shift <= numcnt; shift++) {
81			FLAGW_CF(s & 1);
82			//backup = s; //Save backup!
83			s = (s >> 1) | msb;
84			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
85		}
86		byte tempSF;
87		tempSF = FLAG_SF; //Save the SF!
88		/*flag_szp8((uint8_t)(s & 0xFF));*/
89		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
90		if (!numcnt) //Nothing done?
91		{
92			FLAGW_SF(tempSF); //We don't update when nothing's done!
93		}
94		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
95		{
96			flag_szp32((uint32_t)s); //Affect sign as well!
97			FLAGW_OF(0); //Cleared!
98		}
99		else if (numcnt) //Anything shifted at all?
100		{
101			flag_szp32((uint32_t)s); //Affect sign as well!
102			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
103			{
104				FLAGW_OF(0); //Cleared with count as well?
105			}
106		}
107		break;
108	}
109	op_grp2_cycles32(numcnt, varshift);
110	return (s & 0xFFFFFFFF);
111}

It should give correct results, but for some odd reason it doesn't seem to do so? The 8-bit and 16-bit variants are the same, just with smaller shifts and 0x80* being word or byte sized(0x8000(16-bit) and 0x80(8-bit)). Also they have different wrappings used on the shift counts, according to the 80386 user reference:

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1b;
9	tempCF = FLAG_CF; //Save CF!
10	switch (thereg) {
11	case 0: //ROL r/m8
12		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
13		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
14		for (shift = 1; shift <= numcnt; shift++) {
15			FLAGW_CF((s&0x80)>>7); //Save MSB!
16			s = (s << 1)|FLAG_CF;
17		}
18		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //Only when not using CL?
19		break;
20
21	case 1: //ROR r/m8
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		tempCF = FLAG_CF; //Default: unchanged!
25		for (shift = 1; shift <= numcnt; shift++) {
26			FLAGW_CF(s&1); //Save LSB!
27			s = (s >> 1) | (FLAG_CF << 7);
28		}
29		if (varshift==0) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1)); //Only when not using CL?
30		break;
31
32	case 2: //RCL r/m8
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = FLAG_CF;
37			FLAGW_CF((s&0x80)>>7); //Save MSB!
38			s = (s << 1)|tempCF; //Shift and set CF!
39		}
40		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //OF=MSB^CF, only when not using CL?
41		break;
42
43	case 3: //RCR r/m8
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
46		if (numcnt==1) FLAGW_OF( FLAG_CF^(s >> 7));
47		for (shift = 1; shift <= numcnt; shift++) {
48			tempCF = FLAG_CF;
49			FLAGW_CF(s&1); //Save LSB!
50			s = (s >> 1) | (tempCF << 7);
51		}
52		break;
53
54	case 4: case 6: //SHL r/m8
55		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
56		//FLAGW_AF(0);
57		for (shift = 1; shift <= numcnt; shift++) {
58			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
59			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
60			s = (s << 1) & 0xFF;

…Show last 169 lines

61		}
62		if (numcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
63		if (numcnt) flag_szp8((uint8_t)(s&0xFF));
64		break;
65
66	case 5: //SHR r/m8
67		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
68		if (numcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
69		//FLAGW_AF(0);
70		for (shift = 1; shift <= numcnt; shift++) {
71			FLAGW_CF(s & 1);
72			//backup = s; //Save backup!
73			s = s >> 1;
74			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
75		}
76		if (numcnt) flag_szp8((uint8_t)(s & 0xFF));
77		break;
78
79	case 7: //SAR r/m8
80		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
81		msb = s & 0x80;
82		//FLAGW_AF(0);
83		for (shift = 1; shift <= numcnt; shift++) {
84			FLAGW_CF(s & 1);
85			//backup = s; //Save backup!
86			s = (s >> 1) | msb;
87			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
88		}
89		byte tempSF;
90		tempSF = FLAG_SF; //Save the SF!
91		/*flag_szp8((uint8_t)(s & 0xFF));*/
92		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
93		if (!numcnt) //Nothing done?
94		{
95			FLAGW_SF(tempSF); //We don't update when nothing's done!
96		}
97		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
98		{
99			flag_szp8((uint8_t)s); //Affect sign as well!
100			FLAGW_OF(0); //Cleared!
101		}
102		else if (numcnt) //Anything shifted at all?
103		{
104			flag_szp8((uint8_t)s); //Affect sign as well!
105			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
106			{
107				FLAGW_OF(0); //Cleared with count as well?
108			}
109		}
110		break;
111	}
112	op_grp2_cycles(numcnt, varshift);
113	return (s & 0xFF);
114}
115
116word op_grp2_16(byte cnt, byte varshift) {
117	//word d,
118	INLINEREGISTER uint_32 s, shift, tempCF, msb;
119	INLINEREGISTER byte numcnt;
120	//word backup;
121	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
122	numcnt = cnt; //Save count!
123	s = oper1;
124	tempCF = FLAG_CF; //Save CF!
125	switch (thereg) {
126	case 0: //ROL r/m16
127		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
128		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
129		for (shift = 1; shift <= numcnt; shift++) {
130			FLAGW_CF((s&0x8000)>>15); //Save MSB!
131			s = (s << 1)|FLAG_CF;
132		}
133		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //Only when not using CL?
134		break;
135
136	case 1: //ROR r/m16
137		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
138		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
139		tempCF = FLAG_CF; //Default: unchanged!
140		for (shift = 1; shift <= numcnt; shift++) {
141			FLAGW_CF(s&1); //Save LSB!
142			s = (s >> 1) | (FLAG_CF << 15);
143		}
144		if (varshift==0) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1)); //Only when not using CL?
145		break;
146
147	case 2: //RCL r/m16
148		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
149		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
150		for (shift = 1; shift <= numcnt; shift++) {
151			tempCF = FLAG_CF;
152			FLAGW_CF((s&0x8000)>>15); //Save MSB!
153			s = (s << 1)|tempCF; //Shift and set CF!
154		}
155		if (varshift==0) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //OF=MSB^CF, only when not using CL?
156		break;
157
158	case 3: //RCR r/m16
159		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
160		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
161		if (numcnt==1) FLAGW_OF(FLAG_CF^(s >> 15));
162		for (shift = 1; shift <= numcnt; shift++) {
163			tempCF = FLAG_CF;
164			FLAGW_CF(s&1); //Save LSB!
165			s = (s >> 1) | (tempCF << 15);
166		}
167		break;
168
169	case 4: case 6: //SHL r/m16
170		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
171		//FLAGW_AF(0);
172		for (shift = 1; shift <= numcnt; shift++) {
173			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
174			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
175			s = (s << 1) & 0xFFFF;
176		}
177		if (numcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
178		if (numcnt) flag_szp16((uint16_t)(s&0xFFFF));
179		break;
180
181	case 5: //SHR r/m16
182		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
183		if (numcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
184		//FLAGW_AF(0);
185		for (shift = 1; shift <= numcnt; shift++) {
186			FLAGW_CF(s & 1);
187			//backup = s; //Save backup!
188			s = s >> 1;
189			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
190		}
191		if (numcnt) flag_szp16((uint16_t)(s & 0xFFFF));
192		break;
193
194	case 7: //SAR r/m16
195		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
196		msb = s & 0x8000;
197		//FLAGW_AF(0);
198		for (shift = 1; shift <= numcnt; shift++) {
199			FLAGW_CF(s & 1);
200			//backup = s; //Save backup!
201			s = (s >> 1) | msb;
202			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
203		}
204		byte tempSF;
205		tempSF = FLAG_SF; //Save the SF!
206		/*flag_szp8((uint8_t)(s & 0xFF));*/
207		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
208		if (!numcnt) //Nothing done?
209		{
210			FLAGW_SF(tempSF); //We don't update when nothing's done!
211		}
212		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
213		{
214			flag_szp16(s); //Affect sign as well!
215			FLAGW_OF(0); //Cleared!
216		}
217		else if (numcnt) //Anything shifted at all?
218		{
219			flag_szp16(s); //Affect sign as well!
220			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
221			{
222				FLAGW_OF(0); //Cleared with count as well?
223			}
224		}
225		break;
226	}
227	op_grp2_cycles(numcnt, varshift);
228	return (s & 0xFFFF);
229}

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 93 of 178, by superfury

Posted on 2017-11-10, 01:01

superfury Offline

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Posts: 5910
Joined: 2014-03-08, 11:25
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Just debugged a single 32-bit shift: it sets the CF, then shifts the original value(=1) and ors in the carry flag shifted left by 31, which results in an incorrect 0xffffffff80000000? Shifting more causes those 1-bits to slide into visible range, causing the invalid result? Can anyone tell me why that happens?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 94 of 178, by superfury

Posted on 2017-11-10, 01:28

superfury Offline

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I've just added some 0x7F, 0x7FFF and 0x7FFFFFFF masks to the "(s>>1)" parts (e.g. becoming "((s>>1)&0x7F)"). That was applied to the ROR and RCR instructions. Now the results all match up to the real CPU(all but the flags). 😁 The only bugs still left are (oddly enough) the carry flag and overflow flag not always matching up with an actual CPU?

The attachment porte9.log is no longer available

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 95 of 178, by superfury

Posted on 2017-11-10, 09:17

superfury Offline

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One very important question: does the overflow flag depend on the shift count(needing to be 1), shift instruction(1-shift instruction, CL shift instruction or immediate shift instruction(186+)), the shift count(being any 8-bit number depending on the used value in instruction(1-shift), CL or immediate)) or both? Looking at cape's source code shows that only RCR depends on the instruction type(latter) but all others depend on the shift count only? What is correct?

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Reply 96 of 178, by Jepael

Posted on 2017-11-10, 13:32

Jepael Offline

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superfury wrote:
Just debugged a single 32-bit shift: it sets the CF, then shifts the original value(=1) and ors in the carry flag shifted left by 31, which results in an incorrect 0xffffffff80000000? Shifting more causes those 1-bits to slide into visible range, causing the invalid result? Can anyone tell me why that happens?

https://stackoverflow.com/questions/29538935/ … redirect=1&lq=1

Reply 97 of 178, by superfury

Posted on 2017-11-10, 14:55

superfury Offline

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So indeed, the sign extension is remedied by simply and-ing out the high 33/17/9 bits(sign bit and higher). Now those results are as required.

I've modified all instructions a bit, but for some odd reason the carry and overflow flag(even with ROLi, which shouldn't happen according to documentation!) bits aren't working properly, even though the results in the registers are correct? ROLi, RCLi and RCRi still have overflow bugs. The carry flag bugs appear on ROLr B/W/D, RORr B/W/D, RCRr B/W/D. All other instructions have no problems anymore.

It's strange that the carry bug appears, but the EAX/EDX registers have no differences?
It's also weird that the ROLi seems to set overflow sometimes, even though not a single documentation says it sets the overflow flag in any way?

The attachment porte9.log is no longer available

Anyone knows what's going wrong there?

My documentation:
http://www.felixcloutier.com/x86/RCL:RCR:ROL:ROR.html
http://x86.renejeschke.de/html/file_module_x86_id_273.html
https://pdos.csail.mit.edu/6.828/2014/readings/i386/RCL.htm
http://x86.renejeschke.de/html/file_module_x86_id_285.html

8-bit shifts/rotates:

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt, maskcnt;
5	//word backup;
6	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
7	numcnt = maskcnt = cnt; //Save count!
8	s = oper1b;
9	switch (thereg) {
10	case 0: //ROL r/m8
11		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
12		numcnt = maskcnt;
13		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
14		for (shift = 1; shift <= numcnt; shift++) {
15			FLAGW_CF((s&0x80)>>7); //Save MSB!
16			s = (s << 1)|FLAG_CF;
17		}
18		FLAGW_CF(s); //Always sets CF, according to various sources?
19		if (numcnt==1) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //Only when not using CL?
20		break;
21
22	case 1: //ROR r/m8
23		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		numcnt = maskcnt;
25		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
26		for (shift = 1; shift <= numcnt; shift++) {
27			FLAGW_CF(s&1); //Save LSB!
28			s = ((s >> 1)&0x7F) | (FLAG_CF << 7);
29		}
30		FLAGW_CF(s>>7); //Always sets CF, according to various sources?
31		if (numcnt==1) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1)); //Only when not using CL?
32		break;
33
34	case 2: //RCL r/m8
35		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
36		numcnt = maskcnt;
37		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
38		for (shift = 1; shift <= numcnt; shift++) {
39			tempCF = FLAG_CF;
40			FLAGW_CF((s&0x80)>>7); //Save MSB!
41			s = (s << 1)|tempCF; //Shift and set CF!
42		}
43		if (cnt==1) FLAGW_OF(FLAG_CF^((s >> 7) & 1)); //OF=MSB^CF, only when not using CL?
44		break;
45
46	case 3: //RCR r/m8
47		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
48		numcnt = maskcnt;
49		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
50		if (cnt==1) FLAGW_OF( FLAG_CF^(s >> 7));
51		for (shift = 1; shift <= numcnt; shift++) {
52			tempCF = FLAG_CF;
53			FLAGW_CF(s&1); //Save LSB!
54			s = ((s >> 1)&0x7F) | (tempCF << 7);
55		}
56		break;
57
58	case 4: case 6: //SHL r/m8
59		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
60		numcnt = maskcnt;

…Show last 61 lines

61		//FLAGW_AF(0);
62		for (shift = 1; shift <= numcnt; shift++) {
63			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
64			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
65			s = (s << 1) & 0xFF;
66		}
67		if (maskcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
68		if (numcnt) flag_szp8((uint8_t)(s&0xFF));
69		break;
70
71	case 5: //SHR r/m8
72		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
73		numcnt = maskcnt;
74		if (maskcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
75		//FLAGW_AF(0);
76		for (shift = 1; shift <= numcnt; shift++) {
77			FLAGW_CF(s & 1);
78			//backup = s; //Save backup!
79			s = s >> 1;
80			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
81		}
82		if (numcnt) flag_szp8((uint8_t)(s & 0xFF));
83		break;
84
85	case 7: //SAR r/m8
86		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
87		numcnt = maskcnt;
88		msb = s & 0x80;
89		//FLAGW_AF(0);
90		for (shift = 1; shift <= numcnt; shift++) {
91			FLAGW_CF(s & 1);
92			//backup = s; //Save backup!
93			s = (s >> 1) | msb;
94			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
95		}
96		byte tempSF;
97		tempSF = FLAG_SF; //Save the SF!
98		/*flag_szp8((uint8_t)(s & 0xFF));*/
99		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
100		if (!maskcnt) //Nothing done?
101		{
102			FLAGW_SF(tempSF); //We don't update when nothing's done!
103		}
104		else if (maskcnt==1) //Overflow is cleared on all 1-bit shifts!
105		{
106			flag_szp8((uint8_t)s); //Affect sign as well!
107			FLAGW_OF(0); //Cleared!
108		}
109		else if (numcnt) //Anything shifted at all?
110		{
111			flag_szp8((uint8_t)s); //Affect sign as well!
112			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
113			{
114				FLAGW_OF(0); //Cleared with count as well?
115			}
116		}
117		break;
118	}
119	op_grp2_cycles(numcnt, varshift);
120	return (s & 0xFF);
121}

16-bit shifts/rotates:

1word op_grp2_16(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_32 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt, maskcnt;
5	//word backup;
6	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
7	numcnt = maskcnt = cnt; //Save count!
8	s = oper1;
9	switch (thereg) {
10	case 0: //ROL r/m16
11		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
12		numcnt = maskcnt;
13		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
14		for (shift = 1; shift <= numcnt; shift++) {
15			FLAGW_CF((s&0x8000)>>15); //Save MSB!
16			s = (s << 1)|FLAG_CF;
17		}
18		FLAGW_CF(s); //Always sets CF, according to various sources?
19		if (numcnt==1) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //Only when not using CL?
20		break;
21
22	case 1: //ROR r/m16
23		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		numcnt = maskcnt;
25		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
26		for (shift = 1; shift <= numcnt; shift++) {
27			FLAGW_CF(s&1); //Save LSB!
28			s = ((s >> 1)&0x7FFF) | (FLAG_CF << 15);
29		}
30		FLAGW_CF(s>>15); //Always sets CF, according to various sources?
31		if (numcnt==1) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1)); //Only when not using CL?
32		break;
33
34	case 2: //RCL r/m16
35		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
36		numcnt = maskcnt;
37		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
38		for (shift = 1; shift <= numcnt; shift++) {
39			tempCF = FLAG_CF;
40			FLAGW_CF((s&0x8000)>>15); //Save MSB!
41			s = (s << 1)|tempCF; //Shift and set CF!
42		}
43		if (cnt==1) FLAGW_OF(FLAG_CF^((s >> 15) & 1)); //OF=MSB^CF, only when not using CL?
44		break;
45
46	case 3: //RCR r/m16
47		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
48		numcnt = maskcnt;
49		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
50		if (cnt==1) FLAGW_OF(FLAG_CF^(s >> 15));
51		for (shift = 1; shift <= numcnt; shift++) {
52			tempCF = FLAG_CF;
53			FLAGW_CF(s&1); //Save LSB!
54			s = ((s >> 1)&0x7FFF) | (tempCF << 15);
55		}
56		break;
57
58	case 4: case 6: //SHL r/m16
59		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
60		numcnt = maskcnt;

…Show last 61 lines

61		//FLAGW_AF(0);
62		for (shift = 1; shift <= numcnt; shift++) {
63			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
64			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
65			s = (s << 1) & 0xFFFF;
66		}
67		if (maskcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
68		if (numcnt) flag_szp16((uint16_t)(s&0xFFFF));
69		break;
70
71	case 5: //SHR r/m16
72		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
73		numcnt = maskcnt;
74		if (maskcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
75		//FLAGW_AF(0);
76		for (shift = 1; shift <= numcnt; shift++) {
77			FLAGW_CF(s & 1);
78			//backup = s; //Save backup!
79			s = s >> 1;
80			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
81		}
82		if (numcnt) flag_szp16((uint16_t)(s & 0xFFFF));
83		break;
84
85	case 7: //SAR r/m16
86		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
87		numcnt = maskcnt;
88		msb = s & 0x8000;
89		//FLAGW_AF(0);
90		for (shift = 1; shift <= numcnt; shift++) {
91			FLAGW_CF(s & 1);
92			//backup = s; //Save backup!
93			s = (s >> 1) | msb;
94			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
95		}
96		byte tempSF;
97		tempSF = FLAG_SF; //Save the SF!
98		/*flag_szp8((uint8_t)(s & 0xFF));*/
99		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
100		if (!maskcnt) //Nothing done?
101		{
102			FLAGW_SF(tempSF); //We don't update when nothing's done!
103		}
104		else if (maskcnt==1) //Overflow is cleared on all 1-bit shifts!
105		{
106			flag_szp16(s); //Affect sign as well!
107			FLAGW_OF(0); //Cleared!
108		}
109		else if (numcnt) //Anything shifted at all?
110		{
111			flag_szp16(s); //Affect sign as well!
112			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
113			{
114				FLAGW_OF(0); //Cleared with count as well?
115			}
116		}
117		break;
118	}
119	op_grp2_cycles(numcnt, varshift);
120	return (s & 0xFFFF);
121}

32-bit shifts/rotates:

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_64 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt,maskcnt;
5	//word backup;
6	//if (cnt>0x8) return (oper1b); //NEC V20/V30+ limits shift count
7	numcnt = maskcnt = cnt; //Save count!
8	s = oper1d;
9	switch (thereg) {
10	case 0: //ROL r/m32
11		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
12		numcnt = maskcnt;
13		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
14		for (shift = 1; shift <= numcnt; shift++) {
15			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
16			s = (s << 1)|FLAG_CF;
17		}
18		FLAGW_CF(s); //Always sets CF, according to various sources?
19		if (numcnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF);
20		break;
21
22	case 1: //ROR r/m32
23		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		numcnt = maskcnt;
25		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
26		numcnt = maskcnt;
27		for (shift = 1; shift <= numcnt; shift++) {
28			FLAGW_CF(s&1); //Save LSB!
29			s = ((s >> 1)&0x7FFFFFFF) | (FLAG_CF << 31);
30		}
31		FLAGW_CF(s>>31); //Always sets CF, according to various sources?
32		if (numcnt==1) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
33		break;
34
35	case 2: //RCL r/m32
36		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
37		numcnt = maskcnt;
38		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
39		for (shift = 1; shift <= numcnt; shift++) {
40			tempCF = FLAG_CF;
41			FLAGW_CF((s&0x80000000)>>31); //Save MSB!
42			s = (s << 1)|tempCF; //Shift and set CF!
43		}
44		if (cnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF); //OF=MSB^CF
45		break;
46
47	case 3: //RCR r/m32
48		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
49		numcnt = maskcnt;
50		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
51		if (cnt==1) FLAGW_OF(((s >> 31)&1)^FLAG_CF);
52		for (shift = 1; shift <= numcnt; shift++) {
53			tempCF = FLAG_CF;
54			FLAGW_CF(s&1); //Save LSB!
55			s = ((s >> 1)&0x7FFFFFFF) | (tempCF << 31);
56		}
57		break;
58
59	case 4: case 6: //SHL r/m32
60		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!

…Show last 62 lines

61		numcnt = maskcnt;
62		//FLAGW_AF(0);
63		for (shift = 1; shift <= numcnt; shift++) {
64			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
65			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
66			s = (s << 1) & 0xFFFFFFFF;
67		}
68		if (maskcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }
69		if (numcnt) flag_szp32((uint32_t)(s&0xFFFFFFFF));
70		break;
71
72	case 5: //SHR r/m32
73		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
74		numcnt = maskcnt;
75		if (maskcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
76		//FLAGW_AF(0);
77		for (shift = 1; shift <= numcnt; shift++) {
78			FLAGW_CF(s & 1);
79			//backup = s; //Save backup!
80			s = s >> 1;
81			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
82		}
83		if (numcnt) flag_szp32((uint32_t)(s & 0xFFFFFFFF));
84		break;
85
86	case 7: //SAR r/m32
87		if (EMULATED_CPU >= CPU_NECV30) maskcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
88		numcnt = maskcnt;
89		msb = s & 0x80000000;
90		//FLAGW_AF(0);
91		for (shift = 1; shift <= numcnt; shift++) {
92			FLAGW_CF(s & 1);
93			//backup = s; //Save backup!
94			s = (s >> 1) | msb;
95			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
96		}
97		byte tempSF;
98		tempSF = FLAG_SF; //Save the SF!
99		/*flag_szp8((uint8_t)(s & 0xFF));*/
100		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
101		if (!maskcnt) //Nothing done?
102		{
103			FLAGW_SF(tempSF); //We don't update when nothing's done!
104		}
105		else if (maskcnt==1) //Overflow is cleared on all 1-bit shifts!
106		{
107			flag_szp32((uint32_t)s); //Affect sign as well!
108			FLAGW_OF(0); //Cleared!
109		}
110		else if (numcnt) //Anything shifted at all?
111		{
112			flag_szp32((uint32_t)s); //Affect sign as well!
113			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
114			{
115				FLAGW_OF(0); //Cleared with count as well?
116			}
117		}
118		break;
119	}
120	op_grp2_cycles32(numcnt, varshift);
121	return (s & 0xFFFFFFFF);
122}

Anyone?

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UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 98 of 178, by peterferrie

Posted on 2017-11-10, 18:36

peterferrie Offline

Rank Oldbie

Rank: Oldbie
Posts: 649
Joined: 2008-05-08, 21:54

Overflow happens as you would expect - when the top two bits differ before and after the rotate, using the same algorithm as for add, etc. It happens for all rotate counts, not just 1.
Carry is set to the value of the last bit rotated (e.g. al=0x40, cl=2, rol al,cl -> carry is set).

Reply 99 of 178, by superfury

Posted on 2017-11-10, 19:05

superfury Offline

Rank l33t++

Rank: l33t++
Posts: 5910
Joined: 2014-03-08, 11:25
Location: Netherlands

So when what count is overflow (re)set? The original(cnt), the masked(maskcnt) or the actual shifts(numcnt)?

The setting of the carry bit is already done that way(see code), but still incorrect according to the reference?

Author of the UniPCemu emulator.
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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

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