RDRAM@533 MHz, pt. 2
This is a continuation of the previous post, basically filling in more gaps by studying the datasheet of the DRCGs. Here's a picture of the i840 chipset,
the small ICs marked W134MH on either side are the DRCGs;
The attachment 20180216_i840.jpg is no longer available
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The diagram above is simplified and annotated directly from the datasheet, on the top left is the mainboard's Clock Generator, top center features the DRCG, and the bottom part features the i840's MCH. Also included is the table of truth shown in the DRCGs' datasheet, which overrides what we found in the i840's datasheet (it was more of an implementation guideline in order to accommodate different DRCGs that could be available). The flow is roughly as follows;
- Clockgen generates the FSB and the Refclk, which is FSB/2, and sends them to the MCH and the DRCGs respectively,
- The DRCG receives two input signals: Mult0 and Mult1 (not in the diagram). Depending on their values, it sets different values for 2 variables A and B,
- The DRCG takes the Refclk, multiplies it by A, and divides by B. This generates Busclk. The ratio A/B is the overall multiplier that sets the speed of the RDRAM,
- The MCH takes Busclk and divides it by 4, generating Synclk,
- The MCH now has 2 signals concerning the RDRAM: FSB and Synclk. These operate different parts of the MCH which must be able to talk to each other. Since in general FSB will be different than Synclk, a "Gear Ratio block" is used in order to make a translation from one frequency to the other. The idea is to choose 2 variables, M and N, such that FSB/M and Synclk/N are equal.
- The 2 frequencies generated by the Gear Ratio block are sent back to the DRCG, into a Phase Detector which detects any difference in phase there may be between them and uses it to align the output Busclk. The maximum input frequency for the Phase Detector, as far as I can tell from the datasheet, seems to be 33 MHz.
So, for example, lets take the FSB as 133 MHz, and the values of Mult0 and Mult1 to be 0 and 1 respectively (this is the case of the OR840 running 133 MHz FSB CPUs):
- Refclk is 66 MHz,
- A is 6, B is 1, so Busclk is 400 MHz (which means the RDRAM is running at 400 MHz, or PC-800),
- Synclk is 100 MHz,
- FSB (133 MHz) and Synclk (100 MHz) are different, so the Gear Ratio block chooses M=4 and N=3, yielding FSB/4=Synclk/3=33 MHz (actual vlues of M and N taken from datasheet).
In order to enable RDRAM operation at 533 MHz (PC-1066) we need Mult0 and Mult1 to be 1 and 1 respectively, which can be achieved with the extra jumper described in the previous post. We would have:
- Refclk is again 66 MHz,
- A is 8, B is 1, which yields Busclk of 533 MHz (PC-1066 RDRAM)
- Synclk is 133 MHz,
- FSB and Synclk are equal, Gear Ratio block chooses M=N=4, giving FSB/4=Synclk/4=33 MHz.
The frequency going back to the DRCGs and entering the Phase Detector, 33 MHz, is within spec, trouble may arise within the DRCGs if they are not able to phase align a 533 MHz Busclk, though. I had ordered a spare set of DRCGs for a previous project I was/am working on, and they are drop-in replacements that support 533 MHz so if there is trouble I can substitute them. On the MCH side of things, it hinges on it being able to drive the RDRAM at 533 MHz (assign proper timings, etc), and pick 4 as a value for N in the Gear Ratio block. I know it has nothing to do with the case at hand, but according to the datasheet the i850 operates outside spec when running 533 MHz RDRAM. I hope the i840 is able to do the same.
I still have no clue why Pin2 of the Jumper is connected to the SuperIO chip, but I have not looked into it. More later.
Outrigger: an ongoing adventure with the OR840
QuForce FX 5800: turn your Quadro into a GeForce
