All those registers aren't restored when it repeats. They're saved before each of those repeated instructions starts executing(before every single repeated step during REP CMPS*, so before it starts running and after each time it successfully(without faults) completes said action(that is, e.g. reading memory, storing it in a register and increasing the pointer registers, progressing from the running state to completed state, after which the EFLAGS is checked(and masked according to the CPU mode and CPU type or set(in the case of the 80(1)8X CPUs high 4 bits of FLAGS).
So each time any instruction starts(or repeats) or ends(only during debug exceptions), when starting to fetch new instruction data from the PIQ(and decoding it) or repeating one(a repeated instruction has completed one byte/word/dword and is starting the next byte/word/dword without fetching from the PIQ(keeping it's running state)) said saving of all possibly affected registers and descriptors(and CPL) occurs.
So those saved registers are always saved(using a flag for each and every one of them to mark them saved(except DS/ES/FS/GS and their descriptors, which use a single flag together, as they're always saved together(mainly for the V86 exception trapping to PL0 which affects them)) either before the instruction (or one of it's repeats with the REP prefix) starts, always pointing to the most recent state.
The exceptions to being saved before execution of said instructions are only a few:
- The pre-commit and post-commit state of the TR register and it's descriptor during task switching.
- The post-execution state during single-step exception(triggered by the Trap flag or debug exceptions on the current instructions that are supposed to point to the next instruction), the Single-step exception handler being triggered(with the Resume flag being cleared before the instruction starts).
When any fault occurs(any of the CPU's documented exceptions), any states from the saved information(when their loaded flag is set to a non-zero value(programmed as 1, but any value other than 0 will work) are restored from the image in the CPU's saved registers at the last commit point.