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Dual 1.4 Tualatin MSI 694D Pro

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First post, by Scottmm

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Hope this is in the right area for some support.

I have a recently recapped MSI 694D Pro dual Socket 370 motherboard and a matched pair of modded Pentium III 1.4 Ghz chips.

My issue is that when both chips are installed, the system is unstable BSOD, MEMTEST86 displays memory errors, PC-CHECK shows the second CPU fails SMP test.

I have swapped the CPU positions but same result.

System works great and no issues if I only run 1 CPU (both tested as single).

I used to have dual 866's in this board and no issues.

Has any one had any experience with dual Tualatins in this board?

Reply 1 of 29, by Mamba

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I have exactly the same problem.
No modded bios out there?

Reply 2 of 29, by Scottmm

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Mamba. Can't send pm
No I still have not been able to get the tualatin chips to work in dual configure but non tualatin chips do.
My tualatins came remodded. With underchip pcb. Are yours modded/adaptered?

Reply 3 of 29, by ElectroSoldier

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What is the S-Spec code?
Not all 1400s can SMP.

Reply 4 of 29, by Mamba

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ElectroSoldier wrote on 2024-09-19, 12:25:

What is the S-Spec code?
Not all 1400s can SMP.

AFAIK all P-3s (so 512kb cache) can do SMP….

Reply 5 of 29, by ElectroSoldier

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Mamba wrote on 2024-09-19, 12:42:
ElectroSoldier wrote on 2024-09-19, 12:25:

What is the S-Spec code?
Not all 1400s can SMP.

AFAIK all P-3s (so 512kb cache) can do SMP….

Im assuming you mean P3-s as opposed to P3's?

Pentium III-S Tualatin (512 KB L2 Cache, SMP-capable)
These are the Tualatin processors that support dual-socket SMP (Symmetric Multiprocessing):

Pentium III-S 1400 MHz (1.4 GHz, 512 KB L2 cache)

S-spec codes:
SL657
SL6BY
Pentium III-S 1266 MHz (1.266 GHz, 512 KB L2 cache)

S-spec codes:
SL6BX
SL5QJ
Pentium III-S 1133 MHz (1.133 GHz, 512 KB L2 cache)

S-spec codes:
SL5ZE
SL6CC

Pentium III Tualatin (256 KB L2 Cache, No SMP Support)
Pentium III 1400 MHz (1.4 GHz, 256 KB L2 cache)

S-spec codes:
SL5XL
SL6JP
Pentium III 1266 MHz (1.266 GHz, 256 KB L2 cache)

S-spec codes:
SL5ZF
SL6CB
Pentium III 1200 MHz (1.2 GHz, 256 KB L2 cache)

S-spec codes:
SL5XU
SL5ZF
Pentium III 1133 MHz (1.133 GHz, 256 KB L2 cache)

S-spec codes:
SL5XS
SL5ZB
SL6BW
Pentium III 1000 MHz (1.0 GHz, 256 KB L2 cache)

S-spec codes:
SL5VH
SL5VJ

Yes you need a Pentium III-S to support SMP. The most popular 1400 Tualatin on ebay is the SL5XL and it doesnt support SMP. This is the CPU most people seem to end up with.

Reply 6 of 29, by Mamba

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Yes,
We are always talking about S, when it comes to SMP.

This is the point of the request.

The motherboard seems to be not ok with two S in SMP.
That is why I am asking for a modded bios or for someone able to look at it.

Reply 7 of 29, by ElectroSoldier

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Mamba wrote on 2024-09-19, 13:46:
Yes, We are always talking about S, when it comes to SMP. […]
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Yes,
We are always talking about S, when it comes to SMP.

This is the point of the request.

The motherboard seems to be not ok with two S in SMP.
That is why I am asking for a modded bios or for someone able to look at it.

No were not.
People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs.

After making sure the chips can smp then you should be looking into does the board work with coppermine cpus.

Which we already have the answer to... so you should be looking at the chips can smp.
Its the next logical step.

Reply 8 of 29, by PcBytes

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Dual CPU VIA 694XDPs are generally unstable with 2x Tualatins. It's not isolated to MSI either. ABIT's VP6 also has the same issue, and the report I know of in the VP6's case mentioned both CPUs being SMP capable Tualatins.

The only chipsets that will do Tualatin SMP without issues are Serverworks ch and Intel chipsets. BX would be the best choice over VIA 694. Pro266 also seems to work, likely because of the newer generation of southbridges (VT823x).

Last edited by PcBytes on 2024-09-19, 14:13. Edited 2 times in total.

"Enter at your own peril, past the bolted door..."
Main PC: i5 3470, GB B75M-D3H, 16GB RAM, 2x1TB
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Reply 9 of 29, by Mamba

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ElectroSoldier wrote on 2024-09-19, 13:55:
No were not. People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs. […]
Show full quote
Mamba wrote on 2024-09-19, 13:46:
Yes, We are always talking about S, when it comes to SMP. […]
Show full quote

Yes,
We are always talking about S, when it comes to SMP.

This is the point of the request.

The motherboard seems to be not ok with two S in SMP.
That is why I am asking for a modded bios or for someone able to look at it.

No were not.
People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs.

After making sure the chips can smp then you should be looking into does the board work with coppermine cpus.

Which we already have the answer to... so you should be looking at the chips can smp.
Its the next logical step.

I have a MS-9105 that happily works with a pair of SL5XL....
All P-IIIS can do SMP.

Reply 10 of 29, by Mamba

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PcBytes wrote on 2024-09-19, 14:03:

Dual CPU VIA 694XDPs are generally unstable with 2x Tualatins. It's not isolated to MSI either. ABIT's VP6 also has the same issue, and the report I know of in the VP6's case mentioned both CPUs being SMP capable Tualatins.

Yes I know, probably it is the same problem actually.
And yes, the same CPUs were sitting ona 370DLE wthout issues.

But,
Assuming it is not a fake, here someone was able to:

https://community.hwbot.org/topic/43153-turri … eference-clock/

Reply 11 of 29, by ElectroSoldier

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Mamba wrote on 2024-09-19, 14:11:
ElectroSoldier wrote on 2024-09-19, 13:55:
No were not. People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs. […]
Show full quote
Mamba wrote on 2024-09-19, 13:46:
Yes, We are always talking about S, when it comes to SMP. […]
Show full quote

Yes,
We are always talking about S, when it comes to SMP.

This is the point of the request.

The motherboard seems to be not ok with two S in SMP.
That is why I am asking for a modded bios or for someone able to look at it.

No were not.
People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs.

After making sure the chips can smp then you should be looking into does the board work with coppermine cpus.

Which we already have the answer to... so you should be looking at the chips can smp.
Its the next logical step.

I have a MS-9105 that happily works with a pair of SL5XL....
All P-IIIS can do SMP.

Happily...

The main differences that enable SMP support in processors like the Pentium III-S compared to standard desktop versions lie in a few key areas of the chips design and implementation

1. Multi-Processor Interconnect Support
SMP capable processors have additional logic and hardware support for managing communication between multiple processors. This includes the ability to coordinate cache coherency between processors in a multi-socket system, ensuring that each CPU has an accurate view of the system memory and caches.
The processors use a system bus (FSB) that allows multiple CPUs to share the same memory and I/O subsystems. SMP-capable processors are designed with circuitry to properly handle bus arbitration and allow both CPUs to communicate with the chipset and each other efficiently.

2. APIC (Advanced Programmable Interrupt Controller)
SMP processors generally include a local APIC (Advanced Programmable Interrupt Controller) that allows the CPU to handle and route interrupts in a multi-processor system. The APIC is crucial for directing interrupts to the correct processor in an SMP system, ensuring that system-wide tasks can be shared between CPUs without conflicts.
In single-processor CPUs (which do not support SMP), the APIC may be simplified or absent, as there is no need to manage multiple processors.

3. Microcode and Firmware Differences
SMP-capable CPUs often include specific microcode and firmware-level optimizations that allow them to function in dual-processor configurations. These instructions control how the processor interacts with the system's memory, interrupts, and other processors.
This includes support for cache coherency protocols like MESI (Modified, Exclusive, Shared, Invalid), which ensure that each processor in the system has the correct and up-to-date version of any data in its caches.

4. Processor Validation and Testing for SMP
CPUs intended for SMP configurations typically undergo more rigorous testing to ensure that they can function properly in multi-processor environments. This includes validation for reliability, stability, and compatibility with multiple CPUs sharing resources like memory and I/O.
Even if two CPUs are physically similar (like a Pentium III and Pentium III-S), only those that pass this validation process will have SMP capabilities enabled.

5. Cache Differences
In the case of the Pentium III-S Tualatin processors, there’s also a difference in the L2 cache size. The Pentium III-S processors feature a larger L2 cache (512 KB), which is beneficial in multi-processor systems. This larger cache allows the processor to handle more data locally without having to communicate as much over the system bus, which can improve performance in multi-processor configurations.
However, the larger cache size itself is not the primary enabler of SMP support. It is mainly a performance enhancement that helps in multi-CPU scenarios.

The "S" in Pentium III-S stands for server, and Intel specifically designated these processors for multi-processor servers and workstations. This designation is often more than just a technical difference — it's a matter of positioning. Processors intended for single-processor use are typically not marketed or validated for multi-processor setups, even if they share many of the same physical characteristics.

VIA has always played fast and loose with its chipsets, I have no doubt they built it so people can do exactly what you are doing with it. The use it sees will mean it will probably never need any of the differences between the desktop and server models.

The 694D was a popular board at the time, it was cheap and available which is how I ended up with one. If what you want is possible then the net would be awash with people doing it.
2cpu.com, a site that seems to have been lost to time, might have been cached by the wayback machine. It was always a good place to chat with people who used dualies.

Reply 12 of 29, by Mamba

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ElectroSoldier wrote on 2024-09-19, 19:48:
Happily... […]
Show full quote
Mamba wrote on 2024-09-19, 14:11:
ElectroSoldier wrote on 2024-09-19, 13:55:
No were not. People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs. […]
Show full quote

No were not.
People pick up the SL5XL chips thinking they can SMP with them because theyre P3 1400 CPUs.

After making sure the chips can smp then you should be looking into does the board work with coppermine cpus.

Which we already have the answer to... so you should be looking at the chips can smp.
Its the next logical step.

I have a MS-9105 that happily works with a pair of SL5XL....
All P-IIIS can do SMP.

Happily...

The main differences that enable SMP support in processors like the Pentium III-S compared to standard desktop versions lie in a few key areas of the chips design and implementation

1. Multi-Processor Interconnect Support
SMP capable processors have additional logic and hardware support for managing communication between multiple processors. This includes the ability to coordinate cache coherency between processors in a multi-socket system, ensuring that each CPU has an accurate view of the system memory and caches.
The processors use a system bus (FSB) that allows multiple CPUs to share the same memory and I/O subsystems. SMP-capable processors are designed with circuitry to properly handle bus arbitration and allow both CPUs to communicate with the chipset and each other efficiently.

2. APIC (Advanced Programmable Interrupt Controller)
SMP processors generally include a local APIC (Advanced Programmable Interrupt Controller) that allows the CPU to handle and route interrupts in a multi-processor system. The APIC is crucial for directing interrupts to the correct processor in an SMP system, ensuring that system-wide tasks can be shared between CPUs without conflicts.
In single-processor CPUs (which do not support SMP), the APIC may be simplified or absent, as there is no need to manage multiple processors.

3. Microcode and Firmware Differences
SMP-capable CPUs often include specific microcode and firmware-level optimizations that allow them to function in dual-processor configurations. These instructions control how the processor interacts with the system's memory, interrupts, and other processors.
This includes support for cache coherency protocols like MESI (Modified, Exclusive, Shared, Invalid), which ensure that each processor in the system has the correct and up-to-date version of any data in its caches.

4. Processor Validation and Testing for SMP
CPUs intended for SMP configurations typically undergo more rigorous testing to ensure that they can function properly in multi-processor environments. This includes validation for reliability, stability, and compatibility with multiple CPUs sharing resources like memory and I/O.
Even if two CPUs are physically similar (like a Pentium III and Pentium III-S), only those that pass this validation process will have SMP capabilities enabled.

5. Cache Differences
In the case of the Pentium III-S Tualatin processors, there’s also a difference in the L2 cache size. The Pentium III-S processors feature a larger L2 cache (512 KB), which is beneficial in multi-processor systems. This larger cache allows the processor to handle more data locally without having to communicate as much over the system bus, which can improve performance in multi-processor configurations.
However, the larger cache size itself is not the primary enabler of SMP support. It is mainly a performance enhancement that helps in multi-CPU scenarios.

The "S" in Pentium III-S stands for server, and Intel specifically designated these processors for multi-processor servers and workstations. This designation is often more than just a technical difference — it's a matter of positioning. Processors intended for single-processor use are typically not marketed or validated for multi-processor setups, even if they share many of the same physical characteristics.

VIA has always played fast and loose with its chipsets, I have no doubt they built it so people can do exactly what you are doing with it. The use it sees will mean it will probably never need any of the differences between the desktop and server models.

The 694D was a popular board at the time, it was cheap and available which is how I ended up with one. If what you want is possible then the net would be awash with people doing it.
2cpu.com, a site that seems to have been lost to time, might have been cached by the wayback machine. It was always a good place to chat with people who used dualies.

What can I say.
I can send you pictures if needed.
Anyway I think that only a bios modification may help.
Someone here has this kind of expertise, I know.
I can only hope they read and want to have some fun with it.

Reply 13 of 29, by ElectroSoldier

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Mamba wrote on 2024-09-19, 19:59:
What can I say. I can send you pictures if needed. Anyway I think that only a bios modification may help. Someone here has this […]
Show full quote
ElectroSoldier wrote on 2024-09-19, 19:48:
Happily... […]
Show full quote
Mamba wrote on 2024-09-19, 14:11:

I have a MS-9105 that happily works with a pair of SL5XL....
All P-IIIS can do SMP.

Happily...

The main differences that enable SMP support in processors like the Pentium III-S compared to standard desktop versions lie in a few key areas of the chips design and implementation

1. Multi-Processor Interconnect Support
SMP capable processors have additional logic and hardware support for managing communication between multiple processors. This includes the ability to coordinate cache coherency between processors in a multi-socket system, ensuring that each CPU has an accurate view of the system memory and caches.
The processors use a system bus (FSB) that allows multiple CPUs to share the same memory and I/O subsystems. SMP-capable processors are designed with circuitry to properly handle bus arbitration and allow both CPUs to communicate with the chipset and each other efficiently.

2. APIC (Advanced Programmable Interrupt Controller)
SMP processors generally include a local APIC (Advanced Programmable Interrupt Controller) that allows the CPU to handle and route interrupts in a multi-processor system. The APIC is crucial for directing interrupts to the correct processor in an SMP system, ensuring that system-wide tasks can be shared between CPUs without conflicts.
In single-processor CPUs (which do not support SMP), the APIC may be simplified or absent, as there is no need to manage multiple processors.

3. Microcode and Firmware Differences
SMP-capable CPUs often include specific microcode and firmware-level optimizations that allow them to function in dual-processor configurations. These instructions control how the processor interacts with the system's memory, interrupts, and other processors.
This includes support for cache coherency protocols like MESI (Modified, Exclusive, Shared, Invalid), which ensure that each processor in the system has the correct and up-to-date version of any data in its caches.

4. Processor Validation and Testing for SMP
CPUs intended for SMP configurations typically undergo more rigorous testing to ensure that they can function properly in multi-processor environments. This includes validation for reliability, stability, and compatibility with multiple CPUs sharing resources like memory and I/O.
Even if two CPUs are physically similar (like a Pentium III and Pentium III-S), only those that pass this validation process will have SMP capabilities enabled.

5. Cache Differences
In the case of the Pentium III-S Tualatin processors, there’s also a difference in the L2 cache size. The Pentium III-S processors feature a larger L2 cache (512 KB), which is beneficial in multi-processor systems. This larger cache allows the processor to handle more data locally without having to communicate as much over the system bus, which can improve performance in multi-processor configurations.
However, the larger cache size itself is not the primary enabler of SMP support. It is mainly a performance enhancement that helps in multi-CPU scenarios.

The "S" in Pentium III-S stands for server, and Intel specifically designated these processors for multi-processor servers and workstations. This designation is often more than just a technical difference — it's a matter of positioning. Processors intended for single-processor use are typically not marketed or validated for multi-processor setups, even if they share many of the same physical characteristics.

VIA has always played fast and loose with its chipsets, I have no doubt they built it so people can do exactly what you are doing with it. The use it sees will mean it will probably never need any of the differences between the desktop and server models.

The 694D was a popular board at the time, it was cheap and available which is how I ended up with one. If what you want is possible then the net would be awash with people doing it.
2cpu.com, a site that seems to have been lost to time, might have been cached by the wayback machine. It was always a good place to chat with people who used dualies.

What can I say.
I can send you pictures if needed.
Anyway I think that only a bios modification may help.
Someone here has this kind of expertise, I know.
I can only hope they read and want to have some fun with it.

I have absolutely no doubt you are telling me something that is actually happening.
But at the same time I know the above are facts, that that is how Intel made those chips and the S model is made to work in SMP while the none S model isnt.
There are many chips that should work in SMP but do.

I think your right though I think a BIOS modification will probably make it work. Its not something Ive ever looked into I tend to shy away from VIA chipsets since a Tyan boardI had back in the late 90s early 2000s.
Going by the file creation dates I have for the drivers I had one at the end of 2004. I had Coppermine in mine as had no reason to mess with it. I seem to remember it was disapointing, but that was something to do with the PCI slots that I cant really remember. I ended up swapping it out with a K7D Master-L

Reply 14 of 29, by Scottmm

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Ok my PIII's are PIII-S SL5XL 1.4ghz 512kB models

Reply 17 of 29, by Mamba

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As I said, all S chips are SMP capable.
We should wait for someone who read and help us.

Majestyk or Chkcpu, if they pass by

Reply 18 of 29, by ElectroSoldier

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Mamba wrote on 2024-09-20, 05:10:

As I said, all S chips are SMP capable.
We should wait for someone who read and help us.

Majestyk or Chkcpu, if they pass by

Yes I know, but not all Tualatin chips are P3-S chips 😉

I wouldnt bother with it. I would say its more likely to do with the power than the BIOS settings especially as one works.

Run a pair of coppermine CPUs in it and get a decent board for the Tualatins. There are still some out there.

Reply 19 of 29, by Mamba

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ElectroSoldier wrote on 2024-09-20, 11:44:
Yes I know, but not all Tualatin chips are P3-S chips ;-) […]
Show full quote
Mamba wrote on 2024-09-20, 05:10:

As I said, all S chips are SMP capable.
We should wait for someone who read and help us.

Majestyk or Chkcpu, if they pass by

Yes I know, but not all Tualatin chips are P3-S chips 😉

I wouldnt bother with it. I would say its more likely to do with the power than the BIOS settings especially as one works.

Run a pair of coppermine CPUs in it and get a decent board for the Tualatins. There are still some out there.

Never said this:
“Yes I know, but not all Tualatin chips are P3-S chips“