x86 registers for emulating in a cross-platform way? \ VOGONS

x86 registers for emulating in a cross-platform way?

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First post, by superfury

Posted on 2019-11-09, 20:43

superfury Offline

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I currently have the registers implemented as follows:

1#include "headers/packed.h" //Packed type!
2typedef struct PACKED //The registers!
3{
4
5//Info: with union, first low data then high data!
6	union
7	{
8		struct
9		{
10			#ifdef IS_BIG_ENDIAN
11			word EAXDUMMY;
12			#endif
13			struct
14			{
15				union
16				{
17					word AX;
18					struct
19					{
20						#ifndef IS_BIG_ENDIAN
21						byte AL;
22						byte AH;
23						#else
24						byte AH;
25						byte AL;
26						#endif
27					};
28				};
29			};
30			#ifndef IS_BIG_ENDIAN
31			word EAXDUMMY;
32			#endif
33		};
34		uint_32 EAX;
35	};
36
37	union
38	{
39		struct
40		{
41			#ifdef IS_BIG_ENDIAN
42			word EBXDUMMY;
43			#endif
44			struct
45			{
46				union
47				{
48					word BX;
49					struct
50					{
51						#ifndef IS_BIG_ENDIAN
52						byte BL;
53						byte BH;
54						#else
55						byte BH;
56						byte BL;
57						#endif
58					};
59				};
60			};

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61			#ifndef IS_BIG_ENDIAN
62			word EBXDUMMY;
63			#endif
64		};
65		uint_32 EBX;
66	};
67
68	union
69	{
70		struct
71		{
72			#ifdef IS_BIG_ENDIAN
73			word ECXDUMMY;
74			#endif
75			struct
76			{
77				union
78				{
79					word CX;
80					struct
81					{
82						#ifndef IS_BIG_ENDIAN
83						byte CL;
84						byte CH;
85						#else
86						byte CH;
87						byte CL;
88						#endif
89					};
90				};
91			};
92			#ifndef IS_BIG_ENDIAN
93			word ECXDUMMY;
94			#endif
95		};
96		uint_32 ECX;
97	};
98
99	union
100	{
101		struct
102		{
103			#ifdef IS_BIG_ENDIAN
104			word EDXDUMMY;
105			#endif
106			struct
107			{
108				union
109				{
110					word DX;
111					struct
112					{
113						#ifndef IS_BIG_ENDIAN
114						byte DL;
115						byte DH;
116						#else
117						byte DH;
118						byte DL;
119						#endif
120					};
121				};
122			};
123			#ifndef IS_BIG_ENDIAN
124			word EDXDUMMY;
125			#endif
126		};
127		uint_32 EDX;
128	};
129
130	union
131	{
132		uint_32 ESP; //ESP!
133		struct
134		{
135			#ifdef IS_BIG_ENDIAN
136			word ESPDUMMY;
137			#endif
138			word SP; //Stack pointer
139			#ifndef IS_BIG_ENDIAN
140			word ESPDUMMY; //Dummy!
141			#endif
142		};
143	};
144	union
145	{
146		uint_32 EBP; //EBP!
147		struct
148		{
149			#ifdef IS_BIG_ENDIAN
150			word EBPDUMMY;
151			#endif
152			word BP; //Base pointer
153			#ifndef IS_BIG_ENDIAN
154			word EBPDUMMY; //Dummy!
155			#endif
156		};
157	};
158	union
159	{
160		uint_32 ESI; //ESI
161		struct
162		{
163			#ifdef IS_BIG_ENDIAN
164			word ESIDUMMY;
165			#endif
166			word SI; //Source index
167			#ifndef IS_BIG_ENDIAN
168			word ESIDUMMY; //Dummy!
169			#endif
170		};
171	};
172
173	union
174	{
175		uint_32 EDI; //EDI
176		struct
177		{
178			#ifdef IS_BIG_ENDIAN
179			word EDIDUMMY;
180			#endif
181			word DI; //Destination index
182			#ifndef IS_BIG_ENDIAN
183			word EDIDUMMY; //Dummy!
184			#endif
185		};
186	};
187
188	union
189	{
190		uint_32 EIP; //EIP
191		struct
192		{
193			#ifdef IS_BIG_ENDIAN
194			word EIPDUMMY;
195			#endif
196			word IP; //Instruction pointer; CS:IP=Current instruction; Reset at load of program
197			#ifndef IS_BIG_ENDIAN
198			word EIPDUMMY; //Dummy!
199			#endif
200		};
201	};
202
203	word CS; //Code segment: start of program code; used by instructions and jumps.
204	word DS; //Data segment: beginning of data storage section of memory; used by data manipulation
205	word ES; //Extra segment: used for operations where data is transferred from one segment to another
206	word SS; //Stack segment: stack segment
207	word FS; //???
208	word GS; //???
209
210	union
211	{
212		struct
213		{
214			#ifdef IS_BIG_ENDIAN
215			word EFLAGSDUMMY;
216			#endif
217			word FLAGS; //8086 Flags!
218			#ifndef IS_BIG_ENDIAN
219			word EFLAGSDUMMY; //Dummy!
220			#endif
221		};
222		uint_32 EFLAGS;
223	};
224
225	struct
226	{
227//Tables:
228		DTR_PTR GDTR; //GDTR pointer (48-bits) Global Descriptor Table Register
229		DTR_PTR IDTR; //IDTR pointer (48-bits) Interrupt Descriptor Table Register
230		word LDTR; //LDTR pointer (16-bits) Local Descriptor Table Register (points to an index in the GDT)
231		word TR; //TR (16-bits) Talk Register: currently executing task (points to an index in the GDT)
232
233		union
234		{
235			uint_32 CR[8];
236			struct
237			{
238				uint_32 CR0;
239				uint_32 CR1; //Unused!
240				uint_32 CR2; //Page Fault Linear Address
241				uint_32 CR3;
242				uint_32 CR4; //4 unused CRs until Pentium!
243				uint_32 CR5;
244				uint_32 CR6;
245				uint_32 CR7;
246			}; //CR0-3!
247		}; //CR0-3!
248		union
249		{
250			uint_32 DR[8]; //All debugger registers! index 4=>6 and index 5=>7!
251			struct
252			{
253				uint_32 DR0;
254				uint_32 DR1;
255				uint_32 DR2;
256				uint_32 DR3;
257				uint_32 DR4; //Existant on Pentium+ only! Redirected to DR6 on 386+, except when enabled using CR4.
258				uint_32 noDRregister; //Not defined: DR5 on Pentium! Redirected to DR7 on 386+(when not disabled using CR4).
259				uint_32 DR6; //DR4->6 on 386+, DR6 on Pentium+!
260				uint_32 DR7; //DR5->7 on 386+, DR7 on Pentium+!
261			};
262		}; //DR0-7; 4=6&5=7!
263		union
264		{
265			uint_32 TRX[8]; //All debugger registers! index 4=>6 and index 5=>7!
266			struct
267			{
268				uint_32 TR0;
269				uint_32 TR1;
270				uint_32 TR2;
271				uint_32 TR3;
272				uint_32 TR4;
273				uint_32 TR5;
274				uint_32 TR6;
275				uint_32 TR7;
276			};
277		}; //DR0-7; 4=6&5=7!
278	}; //Special registers!
279} CPU_registers; //Registers
280#include "headers/endpacked.h" //End of packed type!

The issue with this is that with the latest (GCC 9) compiler, it complains about pretty much all of those when storing a pointer or using a pointer to it?

warning: taking address of packed member of 'struct <anonymous>' may result in an unaligned pointer value [-Waddress-of-packed-member]

Is there any way to fix this without having to change all my code in incompatible ways? How should I implement this in a cross-platform cross-compiler way?

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 14, by jmarsh

Posted on 2019-11-09, 21:55

jmarsh Offline

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Get rid of the packed specification. There's no need for it if the layout is correctly ordered.

Reply 2 of 14, by BloodyCactus

Posted on 2019-11-09, 22:29

BloodyCactus Offline

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In a micro interpreter I wrote for a one off thing;

1#include <stdio.h>
2#include <stdint.h>
3#include <stdlib.h>
4#include <string.h>
5#include <inttypes.h>
6
7#pragma pack(1)
8typedef struct udtRegister
9{
10	union
11	{
12		struct { uint32_t ex; };
13#ifndef BIG_ENDIAN
14		struct { uint16_t __ignore0; uint16_t x; };
15		struct { uint16_t __ignore1; uint8_t h; uint8_t l; };
16#else
17		struct { uint16_t x; uint16_t __ignore0; };
18		struct { uint8_t l; uint8_t h; uint16_t __ignore1; };
19#endif
20	};
21} uRegister;
22
23enum eRegs { r_AX = 0, r_CX, r_DX, r_BX, r_SP, r_BP, r_SI, r_DI, r_REGMAX };
24enum eSREgs { r_CS = 0 , r_DS, r_ES, r_SS, r_FS, r_GS, r_SREGMAX };
25
26typedef struct udtRegs
27{
28	uRegister regs[r_REGMAX];
29	uint16_t sregs[r_SREGMAX];
30	uint32_t flags;
31	uint32_t ip;
32} uRegs;
33#pragma pack()
34
35int main(void)
36{
37	uRegs r;
38
39	memset(&r, 0x0, sizeof(uRegs));
40
41	r.regs[r_AX].ex = 0xDEADBEEF;
42
43	printf("eax=0x%08"PRIx32"\n", r.regs[r_AX].ex);
44	printf("ax=0x%08"PRIx16"\n", r.regs[r_AX].x);
45	printf("ah=0x%08"PRIx8"\n", r.regs[r_AX].h);
46	printf("al=0x%08"PRIx8"\n", r.regs[r_AX].l);
47
48	return 0;
49}

1bcactus@workstation.cactus:/tmp$ clang -02 x.c -o x && ./x
2eax=0xdeadbeef
3ax=0x0000beef
4ah=0x000000be
5al=0x000000ef

--/\-[ Stu : Bloody Cactus :: [ https://bloodycactus.com :: http://kråketær.com ]-/\--

Reply 3 of 14, by superfury

Posted on 2019-11-09, 23:29

superfury Offline

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I've changed it a bit in the meantime(I didn't see any replies when I started. Took me all day to adjust all references througout the emulator):

1//General Purpose register support!
2
3#include "headers/packed.h"
4typedef struct PACKED
5{
6	uint_32 reg32;
7	word reg16[2];
8	byte reg8[4];
9} registersplitter;
10#include "headers/endpacked.h"
11
12#ifdef IS_BIG_ENDIAN
13#define GPREG16_LO 1
14#define GPREG8_LO 1
15#define GPREG8_HI 0
16#else
17#define GPREG16_LO 0
18#define GPREG8_LO 0
19#define GPREG8_HI 1
20#endif
21
22enum
23{
24	GPREG_EAX = 0,
25	GPREG_EBX = 1,
26	GPREG_ECX = 2,
27	GPREG_EDX = 3,
28	GPREG_ESP = 4,
29	GPREG_EBP = 5,
30	GPREG_ESI = 6,
31	GPREG_EDI = 7,
32	GPREG_EIP = 8,
33	GPREG_EFLAGS = 9
34}; //All general purpose registers locations in the list!
35
36//Short versions of the registers allocated with the above values as input!
37#define REG8_LO(reg) CPU[activeCPU].registers->gpregisters[reg].reg8[GPREG8_LO]
38#define REG8_HI(reg) CPU[activeCPU].registers->gpregisters[reg].reg8[GPREG8_HI]
39#define REG16_LO(reg) CPU[activeCPU].registers->gpregisters[reg].reg16[GPREG16_LO]
40#define REG32(reg) CPU[activeCPU].registers->gpregisters[reg].reg32
41//Registers version:
42#define REG8R_LO(list,reg) list->gpregisters[reg].reg8[GPREG8_LO]
43#define REG8R_HI(list,reg) list->gpregisters[reg].reg8[GPREG8_HI]
44#define REG16R_LO(list,reg) list->gpregisters[reg].reg16[GPREG16_LO]
45#define REG32R(list,reg) list->gpregisters[reg].reg32
46//Direct version:
47#define REG8D_LO(list,reg) list.gpregisters[reg].reg8[GPREG8_LO]
48#define REG8D_HI(list,reg) list.gpregisters[reg].reg8[GPREG8_HI]
49#define REG16D_LO(list,reg) list.gpregisters[reg].reg16[GPREG16_LO]
50#define REG32D(list,reg) list.gpregisters[reg].reg32
51
52#define REGR_AL(list) REG8R_LO(list,GPREG_EAX)
53#define REGR_AH(list) REG8R_HI(list,GPREG_EAX)
54#define REGR_AX(list) REG16R_LO(list,GPREG_EAX)
55#define REGR_EAX(list) REG32R(list,GPREG_EAX)
56#define REGR_BL(list) REG8R_LO(list,GPREG_EBX)
57#define REGR_BH(list) REG8R_HI(list,GPREG_EBX)
58#define REGR_BX(list) REG16R_LO(list,GPREG_EBX)
59#define REGR_EBX(list) REG32R(list,GPREG_EBX)
60#define REGR_CL(list) REG8R_LO(list,GPREG_ECX)

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61#define REGR_CH(list) REG8R_HI(list,GPREG_ECX)
62#define REGR_CX(list) REG16R_LO(list,GPREG_ECX)
63#define REGR_ECX(list) REG32R(list,GPREG_ECX)
64#define REGR_DL(list) REG8R_LO(list,GPREG_EDX)
65#define REGR_DH(list) REG8R_HI(list,GPREG_EDX)
66#define REGR_DX(list) REG16R_LO(list,GPREG_EDX)
67#define REGR_EDX(list) REG32R(list,GPREG_EDX)
68#define REGR_SP(list) REG16R_LO(list,GPREG_ESP)
69#define REGR_ESP(list) REG32R(list,GPREG_ESP)
70#define REGR_BP(list) REG16R_LO(list,GPREG_EBP)
71#define REGR_EBP(list) REG32R(list,GPREG_EBP)
72#define REGR_SI(list) REG16R_LO(list,GPREG_ESI)
73#define REGR_ESI(list) REG32R(list,GPREG_ESI)
74#define REGR_DI(list) REG16R_LO(list,GPREG_EDI)
75#define REGR_EDI(list) REG32R(list,GPREG_EDI)
76#define REGR_IP(list) REG16R_LO(list,GPREG_EIP)
77#define REGR_EIP(list) REG32R(list,GPREG_EIP)
78#define REGR_FLAGS(list) REG16R_LO(list,GPREG_EFLAGS)
79#define REGR_EFLAGS(list) REG32R(list,GPREG_EFLAGS)
80
81//Direct version
82#define REGD_AL(list) REG8D_LO(list,GPREG_EAX)
83#define REGD_AH(list) REG8D_HI(list,GPREG_EAX)
84#define REGD_AX(list) REG16D_LO(list,GPREG_EAX)
85#define REGD_EAX(list) REG32D(list,GPREG_EAX)
86#define REGD_BL(list) REG8D_LO(list,GPREG_EBX)
87#define REGD_BH(list) REG8D_HI(list,GPREG_EBX)
88#define REGD_BX(list) REG16D_LO(list,GPREG_EBX)
89#define REGD_EBX(list) REG32D(list,GPREG_EBX)
90#define REGD_CL(list) REG8D_LO(list,GPREG_ECX)
91#define REGD_CH(list) REG8D_HI(list,GPREG_ECX)
92#define REGD_CX(list) REG16D_LO(list,GPREG_ECX)
93#define REGD_ECX(list) REG32D(list,GPREG_ECX)
94#define REGD_DL(list) REG8D_LO(list,GPREG_EDX)
95#define REGD_DH(list) REG8D_HI(list,GPREG_EDX)
96#define REGD_DX(list) REG16D_LO(list,GPREG_EDX)
97#define REGD_EDX(list) REG32D(list,GPREG_EDX)
98#define REGD_SP(list) REG16D_LO(list,GPREG_ESP)
99#define REGD_ESP(list) REG32D(list,GPREG_ESP)
100#define REGD_BP(list) REG16D_LO(list,GPREG_EBP)
101#define REGD_EBP(list) REG32D(list,GPREG_EBP)
102#define REGD_SI(list) REG16D_LO(list,GPREG_ESI)
103#define REGD_ESI(list) REG32D(list,GPREG_ESI)
104#define REGD_DI(list) REG16D_LO(list,GPREG_EDI)
105#define REGD_EDI(list) REG32D(list,GPREG_EDI)
106#define REGD_IP(list) REG16D_LO(list,GPREG_EIP)
107#define REGD_EIP(list) REG32D(list,GPREG_EIP)
108#define REGD_FLAGS(list) REG16D_LO(list,GPREG_EFLAGS)
109#define REGD_EFLAGS(list) REG32D(list,GPREG_EFLAGS)

Actual registers in the CPU:

1#include "headers/packed.h" //Packed type!
2typedef struct PACKED //The registers!
3{
4	//First, the General Purpose registers!
5	registersplitter gpregisters[10]; //10 general purpose registers! EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI, EIP, EFLAGS!
6//Info: with union, first low data then high data!
7
8	word CS; //Code segment: start of program code; used by instructions and jumps.
9	word DS; //Data segment: beginning of data storage section of memory; used by data manipulation
10	word ES; //Extra segment: used for operations where data is transferred from one segment to another
11	word SS; //Stack segment: stack segment
12	word FS; //???
13	word GS; //???
14
15	struct
16	{
17//Tables:
18		DTR_PTR GDTR; //GDTR pointer (48-bits) Global Descriptor Table Register
19		DTR_PTR IDTR; //IDTR pointer (48-bits) Interrupt Descriptor Table Register
20		word LDTR; //LDTR pointer (16-bits) Local Descriptor Table Register (points to an index in the GDT)
21		word TR; //TR (16-bits) Talk Register: currently executing task (points to an index in the GDT)
22
23		union
24		{
25			uint_32 CR[8];
26			struct
27			{
28				uint_32 CR0;
29				uint_32 CR1; //Unused!
30				uint_32 CR2; //Page Fault Linear Address
31				uint_32 CR3;
32				uint_32 CR4; //4 unused CRs until Pentium!
33				uint_32 CR5;
34				uint_32 CR6;
35				uint_32 CR7;
36			}; //CR0-3!
37		}; //CR0-3!
38		union
39		{
40			uint_32 DR[8]; //All debugger registers! index 4=>6 and index 5=>7!
41			struct
42			{
43				uint_32 DR0;
44				uint_32 DR1;
45				uint_32 DR2;
46				uint_32 DR3;
47				uint_32 DR4; //Existant on Pentium+ only! Redirected to DR6 on 386+, except when enabled using CR4.
48				uint_32 noDRregister; //Not defined: DR5 on Pentium! Redirected to DR7 on 386+(when not disabled using CR4).
49				uint_32 DR6; //DR4->6 on 386+, DR6 on Pentium+!
50				uint_32 DR7; //DR5->7 on 386+, DR7 on Pentium+!
51			};
52		}; //DR0-7; 4=6&5=7!
53		union
54		{
55			uint_32 TRX[8]; //All debugger registers! index 4=>6 and index 5=>7!
56			struct
57			{
58				uint_32 TR0;
59				uint_32 TR1;
60				uint_32 TR2;

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61				uint_32 TR3;
62				uint_32 TR4;
63				uint_32 TR5;
64				uint_32 TR6;
65				uint_32 TR7;
66			};
67		}; //DR0-7; 4=6&5=7!
68	}; //Special registers!
69} CPU_registers; //Registers
70#include "headers/endpacked.h" //End of packed type!

In the easyregs.h (which is now used in all possible cases, instead of addressing the registers directly):

1//Accumulator register:
2#define REG_AL REG8_LO(GPREG_EAX)
3#define REG_AH REG8_HI(GPREG_EAX)
4#define REG_EAX REG32(GPREG_EAX)
5#define REG_AX REG16_LO(GPREG_EAX)
6
7//Base register:
8#define REG_BL REG8_LO(GPREG_EBX)
9#define REG_BH REG8_HI(GPREG_EBX)
10#define REG_EBX REG32(GPREG_EBX)
11#define REG_BX REG16_LO(GPREG_EBX)
12
13//Counter register:
14#define REG_CL REG8_LO(GPREG_ECX)
15#define REG_CH REG8_HI(GPREG_ECX)
16#define REG_ECX REG32(GPREG_ECX)
17#define REG_CX REG16_LO(GPREG_ECX)
18
19//Data register:
20#define REG_DL REG8_LO(GPREG_EDX)
21#define REG_DH REG8_HI(GPREG_EDX)
22#define REG_EDX REG32(GPREG_EDX)
23#define REG_DX REG16_LO(GPREG_EDX)
24
25//Segment registers
26#define REG_CS CPU[activeCPU].registers->CS
27#define REG_DS CPU[activeCPU].registers->DS
28#define REG_ES CPU[activeCPU].registers->ES
29#define REG_FS CPU[activeCPU].registers->FS
30#define REG_GS CPU[activeCPU].registers->GS
31#define REG_SS CPU[activeCPU].registers->SS
32
33//Indexes and pointers
34#define REG_EDI REG32(GPREG_EDI)
35#define REG_DI REG16_LO(GPREG_EDI)
36#define REG_ESI REG32(GPREG_ESI)
37#define REG_SI REG16_LO(GPREG_ESI)
38#define REG_EBP REG32(GPREG_EBP)
39#define REG_BP REG16_LO(GPREG_EBP)
40#define REG_ESP REG32(GPREG_ESP)
41#define REG_SP REG16_LO(GPREG_ESP)
42#define REG_EIP REG32(GPREG_EIP)
43#define REG_IP REG16_LO(GPREG_EIP)
44#define REG_EFLAGS REG32(GPREG_EFLAGS)
45#define REG_FLAGS REG16_LO(GPREG_EFLAGS)

Also, the packed part is to make it not add padding to each of the byte/word registers. That would cause trouble when using it?

For some reason, this 'improvement' seems to have prevented the Pentium emulation to post (at least until the screen is setup)? POST code is 0x13 on the Compaq Deskpro 386 BIOS.

Edit: Whoops.

1#include "headers/packed.h"
2typedef union PACKED
3{
4	uint_32 reg32;
5	word reg16[2];
6	byte reg8[4];
7} registersplitter;
8#include "headers/endpacked.h"

That needed to be a union to keep working. A struct makes all *X/*L/*H/FLAGS/IP not sharing bits with their 16/32-bit counterparts.

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 4 of 14, by jmarsh

Posted on 2019-11-10, 02:45

jmarsh Offline

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Joined: 2014-01-04, 09:17

superfury wrote:
Also, the packed part is to make it not add padding to each of the byte/word registers. That would cause trouble when using it?

Padding is only added when a member doesn't fall on a boundary that is a multiple of its size. Where do you see that happening?

Reply 5 of 14, by superfury

Posted on 2019-11-10, 14:25

superfury Offline

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I've adjusted to be as follows(for all registers but the CRn/TRn/DRn/GDTR/LDTR registers:

1typedef union
2{
3	uint_32 reg32;
4	word reg16[2];
5	byte reg8[4];
6} registersplitter;

Won't that cause issues with different architectures and (data?) bus widths? Like alignment?

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 6 of 14, by jmarsh

Posted on 2019-11-10, 15:04

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Not as long as the types are properly defined to the correct widths...
It does seem a bit strange to have one type with the size in the name (uint_32), a very vaguely named "word" type and byte which is always 8-bits but isn't called uint_8. What is wrong with just using the stdint.h types?

Reply 7 of 14, by superfury

Posted on 2019-11-10, 15:07

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Also just fixed the 80286 and 80386&80486 LOADALL instruction buffers (for their data loaded from memory to load into the register and descriptor states) to no longer use the packed attribute. The compiler was also complaining about those (when loading them from memory and passing the 16-bit/32-bit item array as a pointer from a packed union).

@jmarsh: The word type and byte type are aliases (using typedef) of the uint16_t and uint8_t types in the general header.

So(from the common emulator framework headers/types.h):

1typedef uint8_t byte;
2typedef uint16_t word;
3typedef int8_t sbyte; //Signed!
4typedef int16_t sword; //Signed!

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 8 of 14, by superfury

Posted on 2019-11-10, 15:09

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I'm wondering though... Won't natural alignment on different processors cause issues with those buffers of LOADALL? Like aligning the word values on 32-bit alignment? That would cause the whole LOADALL structure to malfunction loading it's data into the register/descriptor states(every other variable being cleared)?

The naming of the byte and word types probably still comes from the first programming language I've used(Turbo Pascal 6.0 until I switched to C for PSP, then Windows, then Android software).

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UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 9 of 14, by jmarsh

Posted on 2019-11-10, 22:43

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C guarantees the alignment of a type matches its size (at least for sizes up to the platform's natural word size).

If you have a struct that has a uint16_t member followed by a uint32_t, padding is required to align the latter. The alignment of the struct overall will also be equal to the alignment of its largest member i.e. 4 bytes.

Reply 10 of 14, by BloodyCactus

Posted on 2019-11-10, 23:14

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superfury wrote:
So(from the common emulator framework headers/types.h): […]
Show full quote
So(from the common emulator framework headers/types.h):
1typedef uint8_t byte;
2typedef uint16_t word;
3typedef int8_t sbyte; //Signed!
4typedef int16_t sword; //Signed!

I consider that confusing and obsfucated. Just use <stdint.h> and <inttypes.h> and stick to uint16_t / int16_t etc.

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Reply 11 of 14, by superfury

Posted on 2019-11-10, 23:30

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How is that confusing and obfuscated? The Intel syntax assembly language uses those very same terms (byte, word, dword ptr)? I simply prefixed a 's' for their signed versions. Altbough 32-bit/64-bit variables are an exception(uint_32, int_32, uint_64, int_64).

Those 8/16-bit versions basically have their roots in me originally starting to programming in pascal, which uses byte and word(as does assembly). Those two I still use throughout my projects (to me, actually using uint8_t and uint16_t everywhere is the strange thing). And when you talk about a byte or (double)word value, everyone that knows software knows what you're talking about, don't they?

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 12 of 14, by superfury

Posted on 2019-11-10, 23:36

superfury Offline

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jmarsh wrote:
C guarantees the alignment of a type matches its size (at least for sizes up to the platform's natural word size).

If you have a struct that has a uint16_t member followed by a uint32_t, padding is required to align the latter. The alignment of the struct overall will also be equal to the alignment of its largest member i.e. 4 bytes.

In that case it's good I still have the packed attribute available on the app. Imagine a 48-bit pointer(IDTR/GDTR) being aligned to 32-bit but loaded as 3 16-bit offsets during LIDT/LGDT). Or the byte/word interleaved segment descriptor format(already stripped the bitfields out everywhere due to incompatibility).

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 13 of 14, by jmarsh

Posted on 2019-11-11, 01:07

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BloodyCactus wrote:
I consider that confusing and obsfucated. Just use <stdint.h> and <inttypes.h> and stick to uint16_t / int16_t etc.

Completely agree, they are the "standard" types for a reason.

superfury wrote:
when you talk about a byte or (double)word value, everyone that knows software knows what you're talking about, don't they?

No.
Is a "byte" signed or unsigned?
A "word" is a generic term for a multibyte value. Is it 2 bytes? 4 bytes? 8 bytes? It makes sense if you also use dword, oword etc. to differentiate the sizes but you're not doing that.

superfury wrote:
In that case it's good I still have the packed attribute available on the app.

Sure if you insist on defining far pointers as structs, but you don't need it for register definitions because there's no padding required.

Reply 14 of 14, by BloodyCactus

Posted on 2019-11-11, 01:17

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superfury wrote:
How is that confusing and obfuscated? The Intel syntax assembly language uses those very same terms (byte, word, dword ptr)? I simply prefixed a 's' for their signed versions. Altbough 32-bit/64-bit variables are an exception(uint_32, int_32, uint_64, int_64).

to me, your writing C, not Assembler. Use C conventions, the c library gives you those in stdint.h + inttypes.h
but obviously, use whatever its your app.

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