I was looking into this same issue (in part wondering how much under/over-volting SRAM impacts stability at high timing speeds) and trying to work out whether later, 3~3.8V compliant 486 boards used 3.3V rated cache RAM or stuck with 5V rated stuff. The 3.3V rated and 5V tolerant RAM would be ideal, but seems less common and may have been more expensive, but common 5V rated SRAM running undervolted to 3.3V (if a particular board/chipset ran I/O and supply voltages to CPU and cache at common levels, 5V RAM would be out of spec and potentially slower operating than designed).
Plus, I thought Socket 7 boards at least ran cache, DRAM, and chipset supply voltage at the I/O voltage level (except for explicit 5V EDO/FPM DRAM support) hence greater bus and RAM stability at higher I/O voltages, including heavier overvolting supported on some overclocking-friendly boards. (like the 4.0V setting on the Asus P5A and P5A-B) Or maybe 5V supply was used for DRAM and asynch cache RAM with the switch to common supply and I/O voltage coming with pipeline burst cache.
That might explain the poor performance of 15 ns cache RAM at 60-66 MHz on 486 boards with 3V CPUs, while 15 ns seems to be the common choice for Socket 4 pentium surface-mounted cache RAM. (the 5.27V spec cited for stable 66 MHz operation on Intel Batman boards might even have something to do with that rather than just CPU stability)
OTOH it might simply be the trends for 486 boards to use the same speed SRAMs for both cache and TAG RAM, while the TAG RAM might need to be a good deal faster to operate at the bus speed limits of the cache itself (plus other variables depending on WB vs WT cache operation).
The same goes for DRAM compatibility, though 5V tolerant, 3.3V rated FPM and EDO DRAM seems somewhat more common, I'm not actually sure how Socket 3/5/7 boards handled that. (unless it was standard to have cache and DRAM both at 5V supply across the board, and just the CPU's I/O end at 3.x V)
Looking at the AS7C3256 datasheet, it's indeed got a 3.3V rated supply and I/O (3.0 min, 3.6 max) for standard operation, and 5.0V listed for absolute maximum rating, but that's probably close enough to make it reasonably 5V tolerant in real-world use, just at the warranty-voiding levels of close tolerances with typical voltage regulation limits at 5.25V. (albeit the 5V lines on a lot of AT/ATX power supplies, or the output board-level +5V is quite often in the 4.8-4.9V range, as is the output of a lot of 7805 style linear regulators on old game consoles and home computers I've tested; an old AT PSU I have reads around 5.2V open-circuit voltage, but that's not necessarily representative of voltage under load, even without further board-level regulation)
However, that doesn't extend to all 3.3V rated similar SRAMs, and some have the absolute maximum rating capped well below 5V. The IS61LV256 datasheet (or the 2009 dated version) cites +4.6V as the absolute maximum vs 7.0V max for the 5V rated IS61C256. (7.0V being pretty typical for 5V rated components)
http://pdf.datasheetcatalog.com/datasheet_pdf … 61LV256-8TI.pdf
Also, an older 1996 copyright datasheet also lists +4.6V
https://datasheetspdf.com/pdf-file/247232/ETC/61LV256/1
That one, unlike the newer one, also lists DIP versions being available, which would be more relevant for the majority of 486 boards (and a good deal of Socket 5 boards) back then. Albeit 32-pin 64kx8-bit SRAMs were more common for the very late PCI based baby AT 486 boards. (though 32kx8-bit chips could still be installed for 128kB cache rather than 256) I know some models also opted for surface-mounted 32kx8-bit chips in the older dual 128kB bank configuration. (which I'd assume also has potential speed/latency advantages with bank-interleaving enabled, like 2-1-1-1 timing where a single bank would be limited to 2-2-2-2 using the same speed SRAM)
That sounds like it'd probably tolerate running at +5V for a good while, but would have a significantly reduced lifespan (probably moreso with poorer cooling), maybe a bit like running AM5x86 chips at 5V. Indeed, the .35 micron 5x86 datasheet lists the same +4.6 maximum supply voltage, but then so does the .5 micron AM486DX4, so the real-world absolute maximum margins might vary a bit more than official speed bins (and in the case of SRAMs, there might be mixes of smaller/newer process downbinned chips and older/larger process ones so having a common operational restriction across the board would be safer and much easier for manufacturer yield management; likewise some 5V rated parts could be down-binned newer/intermediate process chips generally accepted as 5V tolerant)
see:
http://datasheets.chipdb.org/AMD/486_5x86/19160D.pdf
http://pdf.datasheetcatalog.com/datasheet/Adv … ices/mXxryq.pdf
And even the older (I think .8 or .7 micron) 3V rated AM486DX2 datasheet lists the same 4.6V absolute maximum rating. (and some sources state or imply that the same process was used for AMD's 5V and 3.3V rated DX2 parts, so they should all be 5V tolerant)
http://datasheets.chipdb.org/AMD/486_5x86/19200D.pdf
Plus that sort of blanket specification (like with the older 5Vcc and +7V absolute rating that spanned a couple decades worth of chip fab processes) makes it much easier to have industry standard replacement parts between manufacturers and for obsolete models.
Interestingly, SGST's datasheet for their Cyrix based DX4 cites 4.6V max on Vcc, but also lists 6.0V max on any pin (with respect to Vss), which makes it sound like the process used is likely 5V tolerant as well, but that they're generally complying with the de facto industry standard 4.6V figure.
https://www.digchip.com/datasheets/download_d … number=ST486DX4
Cyrix's 5x86 datasheet cites 4.0Vcc max but the same 6.0V on any pin in the absolute maximum ratings.
http://datasheets.chipdb.org/Cyrix/5x86/5X-ABDB.PDF
The ST5x86 sheet has the same 4.0Vcc and 6V on any pin ratings listed.
But with SRAM, especially buying new/used/old-stock parts these days, you could have a very mixed bag compared to at least mostly consistent manufacturing processes for vintage processors. (even if some seem to be somewhat nebulous on the exact process or even chip fab used) So guessing at possible out-of-spec tolerance would be even harder than technicians doing that 20+ years ago.
On top of all that, bear in mind that voltage restrictions can also be chosen for power draw and heat dissipation reasons, so the actual limits of the IC itself (and damage due to electron migration, etc, degrading the transistors or interconnect) might not be so obvious either. Moreso since RAM (and older CPUs) were expected to operate without heatsinks, and CPUs that were expected to use heatsinks didn't have large or elaborate heatsink+fan combos in mind. (apparently a big part of the Socket 4 Pentium's teething troubles, too ... probably part of the original 486DX-50's troubles as well)
