PC-Engineer wrote on 2020-05-27, 05:55:
In 486 world PCI is not in general faster than VLB. Good VLB boards are equal to good PCI boards at same clock. And measuring the Bus-Speed with Speedsys is not the best method to find out the true bus performance.
I would be very interested in some actual numbers backing this up. Sounds rather implausible given how faster, more capable graphics and disk controller chipsets only exist in PCI form. We're not discussing bus speeds here, but whole-system performance.
PC-Engineer wrote on 2020-05-27, 05:55:
In my experiences with comparing L1 cache strategies (using intel/AMD DX2 and DX4 with SIS and UMC chipsets), L1WB makes nearly zero to L1WT in Application-Benchmarks (Doom, Quake, PCP-Bench, Winstone), if you have 256kB or more L2 in WB. Surprisingly, in case of intel DX2 the L1WB/L2WB was a little bit slower than L1WT/L2WB.
I think you shouldn't be mixing Intel and AMD chips in your tests as AMD chips are significantly slower at floating point math than Intel chips at the same clockspeed.
WB L1 on an Intel chip gives you up to a 15% boost in FPU-intensive workloads, so I am actually surprised at your results. Quake especially, since it's so FPU-heavy.
PC-Engineer wrote on 2020-05-27, 05:55:
The 486 WB CPUs from intel where intended for low cost systems without L2 cache.
Where did you read that? That really makes no sense to me. A system with no L2 would be dog-slow regardless of the L1 mode and by the time the DX4 WB appeared (October 1994) cache was cheap.
Having a DX4 WB in a L2-less system would literally make as much sense as having a Ferrari engine in a Fiat 126.
PC-Engineer wrote on 2020-05-27, 05:55:
@starcube
Its a beautiful and well designed 486 system! But why you chose a 486 ALI chipset for a dream system? 😉
Because if you read the datasheets, only the ALi chipset is designed to actually take advantage of EDO DRAM. While late SiS and UMC will boot with EDO DRAM (early revisions will not), they don't actually support EDO data rates and just run it as FPM. 😉