After implementing the APIC registers and it's read-only registers(the LAPIC writable registers being fully writable atm), Windows NT 4.0 tries to disable the PIC(setting the mask registers to 0xFF) and use the APIC/LAPIC instead.
But since the APIC doesn't have anything emulated yet, it will hang the OS which never receives any interrupts anymore.
So i will have to actually do some implementing on the APIC's IRQ lines and interrupt handling.
Just implemeted some basic edge-triggered IRQ support for the APIC.
Edit: Eventually moved the IO APIC to it's proper address. Now Windows NT 4.0 seems to actually try to use it? I see it's using the 8th redirection entry(low dword 48D1h, high dword 1000000h).
Edit: It maps it to interrupt D1h apparently? Is that IRQ8?
Although it eventually hanged because the IRQ wasn't received anymore(IRQ8 that is) because it's never acnowledged?
Just implemeted the pass-through scheme with priorities on the APIC.
So now, the IO APIC will constantly check if it can perhaps send it's unmasked IRQ lines that are raised by the hardware(for now always in edge-triggering mode). The level mode is currently ignoring the inputs.
When it notices that it might be able to send it to the Local APIC, it will try to find the highest prioirity IRQ to send to the Local APIC. If it's able to, it lowers the raised IRQ signal bit and sets the IRR bit of the CPU's Local APIC(essentially the message handling between the Local APIC and the IO APIC).
Then, the Local APIC does nothing more than, once for each instruction, check if it has IRRs that have ISRs unmasked. If so, it finds the highest priority bit that's set and simply fires the IRQ on the CPU(setting the ISR and clearing the IRR along the way).
The only thing the CPU does is sending the B0 command with value 00000000h(32-bit dword) to clear the ISR, after which on the next instruction with CPU interrupts enabled the local APIC will start checking the IRRs and ISRs again until a new interrupt is pending again.