What happens with the LVT or IO APIC delivery bit when a request is lowered(e.g. INTR is lowered) or kept raised(not changing) and acnowledged to the hardware(INTA presumably doesn't lower INTR when others are still pending)?
Author of the UniPCemu emulator.
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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io
Well, Windows 95 revealed an APIC issue with multiple pending IRQs. It would INTA the first one, then until INTR was lowered and raised again(re-registering the request), it wouldn't register it anymore, since it only triggered the delivery bit when lowering/raising INTR(which doesn't lower in that case).
So, when handling a APIC-based hardware interrupt or LVT, it would need to re-check all raised/lowered connected INTR/NMI/IR lines to properly handle the effect of keeping the delivery bit set properly.
Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io