512MB is the max it will do, chipset limitation.

computerguy08 wrote on 2021-01-26, 22:48:

512MB is the max it will do, chipset limitation.

Yeah, but apparently the tx is limited to 256 but that didn’t stop repoman from getting 384 recognized (failed to boot though probably timing or memory setting issue)

Repo Man11 wrote on 2021-01-20, 03:35:

I was sure that 256 was the limit, but I decided to try for myself. Starting with a 256 PC133 in one slot that I've been using for some time, trying any of the other 256 meg sticks of SDRAM I have in slot 2 would just cause it to beep without posting. But there were a couple of different 128s that it recognized and would POST with, recognizing 384 (393216)! But in both cases, it will only boot up in Safe Mode, and I've been content with the performance of this machine with 256 megabytes so that's the end of the experiment for me.

Asus TXP4 with a K6-3+.

The Intel HX chipset can do 512 MB RAM - all cachable (depending on the L2 cache SRAM size and Tag-RAM) and that´s it´s great advantage and the reason it was appreciated back in the days despite it´s lack of supporting SDRAM.

majestyk wrote on 2021-01-27, 06:49:

The Intel HX chipset can do 512 MB RAM - all cachable (depending on the L2 cache SRAM size and Tag-RAM) and that´s it´s great advantage and the reason it was appreciated back in the days despite it´s lack of supporting SDRAM.

Do you see any problem with me configuring 512 as 128 x 4 or will I have to do 64 x 8

If 128 x 4 works which slots should I use? Lowest 4? Or right or left or top four?

I’m going thinking bottom four right? Cause closest to chipset

According to the manual it would be 64x8.
But if you have 128MB sticks at hand you can give it a try by populating bank 0 and bank 1. (The 4 slots on the left)

Sphere478 wrote on 2021-01-27, 07:08:

Do you see any problem with me configuring 512 as 128 x 4 or will I have to do 64 x 8

If 128 x 4 works which slots should I use? Lowest 4? Or right or left or top four?

I’m going thinking bottom four right? Cause closest to chipset

I don't know the details of whether or not you'll be able to use 128MiB modules, but I would recommend using slots that are farthest away from the chipset, as this will give the best electrical termination of the signals, not having a stub of pcb trace afterwards.

H3nrik V! wrote on 2021-01-27, 07:15:

Sphere478 wrote on 2021-01-27, 07:08:

Do you see any problem with me configuring 512 as 128 x 4 or will I have to do 64 x 8

If 128 x 4 works which slots should I use? Lowest 4? Or right or left or top four?

I’m going thinking bottom four right? Cause closest to chipset

I don't know the details of whether or not you'll be able to use 128MiB modules, but I would recommend using slots that are farthest away from the chipset, as this will give the best electrical termination of the signals, not having a stub of pcb trace afterwards.

This answer surprises me. 🤔 very well. Top slots it is!

Btw, I believe the way it’s wired it has four banks. So using the closer slots won’t have wires hanging out..? As the top slots are on their own banks

As far as I recall, the memory banks must be populated with identical pairs of RAM, starting with bank 0, then bank 1, bank 2, bank 3.
This would mean the 4 slots on the left.
Just try it.

majestyk wrote on 2021-01-27, 07:27:

As far as I recall, the memory banks must be populated with identical pairs of RAM, starting with bank 0, then bank 1, bank 2, bank 3.
This would mean the 4 slots on the left.
Just try it.

Would definately make sense too ..

Sphere478 wrote on 2021-01-27, 07:16:

H3nrik V! wrote on 2021-01-27, 07:15:

Sphere478 wrote on 2021-01-27, 07:08:

Do you see any problem with me configuring 512 as 128 x 4 or will I have to do 64 x 8

If 128 x 4 works which slots should I use? Lowest 4? Or right or left or top four?

I’m going thinking bottom four right? Cause closest to chipset

I don't know the details of whether or not you'll be able to use 128MiB modules, but I would recommend using slots that are farthest away from the chipset, as this will give the best electrical termination of the signals, not having a stub of pcb trace afterwards.

This answer surprises me. 🤔 very well. Top slots it is!

Btw, I believe the way it’s wired it has four banks. So using the closer slots won’t have wires hanging out..? As the top slots are on their own banks

Look at it like water - you have a pipe leading from the chipset to the slots. If using the closest slots, you'll have a pipe to the slot and then an "appendix" (just like the body part), and when you move water back and forth between the chipset and memory slot, you'll have a lot of turbulence from the appendix'ed pipe .. Does that make sense?

Oh, I hadn't thought of that it was banks, that needed to be filled all together separately. In that case, it doesn't matter with regards to impedance matching and reflections. Then you should follow what the chipset specifications are.

H3nrik V! wrote on 2021-01-27, 07:53:

Sphere478 wrote on 2021-01-27, 07:16:

Btw, I believe the way it’s wired it has four banks. So using the closer slots won’t have wires hanging out..? As the top slots are on their own banks

Oh, I hadn't thought of that it was banks, that needed to be filled all together separately. In that case, it doesn't matter with regards to impedance matching and reflections. Then you should follow what the chipset specifications are.

Like described by Majestyk

majestyk wrote on 2021-01-27, 07:27:

As far as I recall, the memory banks must be populated with identical pairs of RAM, starting with bank 0, then bank 1, bank 2, bank 3.
This would mean the 4 slots on the left.
Just try it.

yes, it’s 64 bit so simms have to be in pairs of two you can install different pairs but the pairs have to be intentional or at least the same size example bank 0 can get 16mb x 2 and bank 1 can get 4mb x 2 and that will be fine for 40mb total memory but you can’t do bank 0 as 4mb + 16mb and bank 1 as 4mb + 16mb that won’t work.

So the controller likes to start at bank 0? And populating only bank 0 and 2 would cause a performance hit? Does it have to daisy chain through 1 or something to get to 2? Does that cost a clock cycle or something to do? Slowing down access time?